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Consider the following synchronous buck converter:

enter image description here

where Q1 is the high-side and Q2 the low-side

enter image description here

(https://fscdn.rohm.com/en/products/databook/applinote/ic/power/switching_regulator/buck_converter_efficiency_app-e.pdf)

When the high side Q1 device turns on, it will charge up the C_OSS of the low-side Q2 device. In the app note above, it states that this charge is usually ignored because eventually that charge on the C_OSS of Q2 will flow to the load and hence not be wasted.

However, and this is my question, when C_OSS of Q2 is being charged up in the first place (i.e. when Q1 high-side turns on), that is essentially a voltage source Vin charging a capacitor C_OSS of Q2 which is inherently a lossy operation (Is the 50% loss of energy when charging a cap from a battery a set rule in stone?) The discharging of Q2 C_OSS is loseless due to the inductor discharging it, however the charging up of Q2 C_OSS is not via the inductor, it is via the Vin and hence it should be lossy.

Why is the loss associated with the initial C_OSS charging of Q2 (low-side) when Q1 (high-side) turned on being ignored here?

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    \$\begingroup\$ When the high-side switch turns off, the low-side body diode freewheels the inductor current immediately and you have a \$V_f\$ across the low-side switch. Then, if \$Q_2\$ turns on after a bit of deadtime, you have conditions for ZVS as mentioned in the text. When the hi-side switch turns back on, then, assuming CCM, the current is still freewheeling in low side via the body diode if \$Q_2\$ has been safely turned off prematurely. Therefore, it is mainly the reverse recovery loss of the body that you see inflicted to \$Q_1\$ but certainly \$C_{OSS}\$ also, perhaps a lower contributor however. \$\endgroup\$ Commented Dec 4, 2023 at 15:42
  • \$\begingroup\$ @VerbalKint Thanks. Right, so the way I understand the impact of the Q2 C_OSS is as follows: 1. To charge up the Q2 C_OSS, that charge originally comes from Vin and that charging mechanism is lossy as it is a voltage source charging a capacitor (capacitor paradox, independent of R and all that stuff). 2. The charge that Q2 C_OSS does store will be dissipated to the output in the next dead-time state and hence discharge the switch node to 0V then to -0.7V once Q2 body diode conducts. \$\endgroup\$
    – muosac
    Commented Dec 4, 2023 at 16:17
  • \$\begingroup\$ So point 1 above is a loss, however the point 2 above is just charge that ends up at the load, so it is not a loss, it just happens in two steps, first stored on Q2 C_OSS, then sent to the output. \$\endgroup\$
    – muosac
    Commented Dec 4, 2023 at 16:18

1 Answer 1

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Is the 50% loss of energy when charging a cap from a battery a set rule in stone?

Yes it is.

Why is the loss associated with the initial C_OSS charging of Q2 (low-side) when Q1 (high-side) turned on being ignored here?

It shouldn't be ignored; it's a real loss.

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  • \$\begingroup\$ Got it. One more example if you could let me know if my understanding is correct: I turn on Q1, 150nC flows out of Vin supply, 75nC is dissipated in the resistive elements and 75nC goes to charge up the Q2 C_OSS to Vin. So far, 75nC has been wasted. In the next dead-time phase when Q1 and Q2 are both off, Q2 C_OSS is still initially at Vin and the load will begin to discharge this, so that 75nC will flow out of Q2 C_OSS, discharging it to 0V and flow to the load, this is not wasted charge as the charge went to the output and was discharged via an inductor. \$\endgroup\$
    – muosac
    Commented Dec 4, 2023 at 16:25
  • \$\begingroup\$ You can't realistically waste charge because charge is made of electrons and they are still around. You can lose the energy associated with charge though. That's what's happening here; half the energy is lost charging up the DS capacitance. In a synchronous converter (that's what you have shown) there is a tiny little bit of time (several nano seconds to maybe 30 nano seconds typically) where neither MOSFET is turned off and, because it's such a small length of time so we can ignore that.... \$\endgroup\$
    – Andy aka
    Commented Dec 4, 2023 at 16:39
  • \$\begingroup\$ ....But, if you are considering using the lower MOSFET as an ideal diode (in DCM) then, you can make an argument for that energy not being lost. If we are done here, please take note of this: What should I do when someone answers my question. If you are still confused about something then leave a comment to request further clarification. \$\endgroup\$
    – Andy aka
    Commented Dec 4, 2023 at 16:40

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