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In my computer logic and design class, we have gone over the different types of flip flops and their representations. I understand what the goal of the master-slave configuration is but I am having trouble figuring out how it works.

Given the JK Flip Flop Below:

enter image description here

Let the current state of the flip be [CLK = 0, J = 0, K = 1, P = 1, Q = 0], This would make both S1 and R1 equal to 0, resulting in P = 1. But J = 0, K = 1 should be a reset operation. Doesn't this contradict what a JK flip flop is supposed to do? Are there methods to prevent this from happening?

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  • \$\begingroup\$ please add a link to the source of the logic diagram into your question \$\endgroup\$
    – jsotola
    Dec 5, 2023 at 1:22
  • \$\begingroup\$ find a diagram that is all discrete gates ... it may help you to understand the signal flow \$\endgroup\$
    – jsotola
    Dec 5, 2023 at 1:23
  • \$\begingroup\$ Gates should not be "nand" gates ... \$\endgroup\$
    – Antonio51
    Dec 5, 2023 at 9:24
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    \$\begingroup\$ @Antonio51 Which NAND gates? \$\endgroup\$ Dec 5, 2023 at 10:59
  • \$\begingroup\$ Where did you obtain this circuit, or did you invent it yourself? It seems to be wrong, as it exhibits strange behaviour, for example outputting a 1-cycle 1 when starting from the described situation. (Please note that this is not a forum, edit your question to clarify.) \$\endgroup\$ Dec 5, 2023 at 13:43

2 Answers 2

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As long as S1 = 0 and R1 = 0, the first flip flop will keep its state.

Your comment:

What would happen though if while in the LOW clock signal a J=1, K = 0 signal is sent, setting P to 1, then a J=0,K=1 signal is sent. That would create the situation I described, correct?

Correct, but this does not contradict the definition. By the sequence you describe you set the first flip flop (intermediate S1 = 1 and R1 = 0), but because of Q = 0, the K = 1 never gets to the flip flop, always R1 = 0.

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No, in a JK flip flop, on a rising clock edge, J=0 K=0 results in Qn+1=Qn and J=0 K=1 results in Qn+1 =0

J=0, K=1 is the reset
J=0, K=0 maintains the output.

In your example above, your conditions are invalid. If Qn = 0, then Pn-1 = 0 and P'n-1 = X. A value of P=1 will produce Q=1 when the clock edge appears.
Ok so for the conditions Qn=0, and therefore Pn=0, then we apply CLKn+1 = 0, Jn+1=1, Kn+1=0, S1 = Q' & J & CLK' = 0, setting Pn+1 = 1. While Q = 0, R1 = 0, so the SR flip flop cannot be reset.
When we apply CLKn+2 = 0, Jn+2 = 0, Kn+2 = 1, Pn+2=1 still because the flip flop cannot be reset until it rises high. When the next CLK edge appears, Q = 1

This transition of changing J and K inbetween I think is invalid, and hence why it produces this unexpected behaviour.

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  • \$\begingroup\$ Sorry, that first part was a typo, J=0, K=1 is the reset. What would happen though if while in the LOW clock signal a J=1, K = 0 signal is sent, setting P to 1, then a J=0,K=1 signal is sent. That would create the situation I described, correct? \$\endgroup\$ Dec 4, 2023 at 23:30
  • \$\begingroup\$ See my edit, I understand your point now \$\endgroup\$
    – LordTeddy
    Dec 5, 2023 at 11:46

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