I want to scale the amplitude (the High level) of a PWM signal by switching the output of a DAC. I am using MCP4822 12-bit DAC to generate 0 - 2.048V and switching it using a SN74LVC1G3157 analog SPDT switch. The schematic is simple:

Switching an analog switch by PWM signal to scale its amplitude using a DAC

The PWM input signal is of 1-25 MHz range with 50% duty cycle. That is Ton/ Toff is in the range 500-20ns.

According to the datasheet, the analog BW of SN74LVC1G3157 is 300 MHz that corresponds to a rise time of 0.35/300M ~1.1 ns. The propagation delay is ~1 ns. The ON state capacitance is ~15 pF.

While measuring the output of the switch using a DSO + 10x probe I see a slow rise of the output voltage and it takes ~100 ns to settle to the input DC level when the switch on. Please see the DSO traces (yellow = input PWM, blue = output of the switch, A port) at 100k, 1M, 5M & 10 MHz frequencies of the input PWM.

enter image description here

How can I reduce this settling time? I am wondering that the specifications of the switch is way faster than the settling time that I am getting. Do I have excessive stray capacitance? I was prototyping the circuit on a perfboard and probe the signals with ground spring. The analog switch is soldered on this generic SOIC/SSOP to DIP converter that I am using. The completeness I show a picture of the (poor? ) setup:

enter image description here

Finally I will be making a PCB anyway, but for now this is the best I could to.

  • \$\begingroup\$ With no load, it would be difficult. Use a 50 Ohm load if possible. \$\endgroup\$
    – Antonio51
    Commented Dec 6, 2023 at 13:52
  • \$\begingroup\$ I indeed tried adding a 50 ohm load. In fact the BW specified in the datasheet assumes a 50 ohm load. Adding a 50 ohm load just reduced the amplitude and the settling time remained unchanged! \$\endgroup\$
    – itheo92
    Commented Dec 6, 2023 at 14:05

2 Answers 2


The ringing you see at both rising and falling edges is caused by the switch or by the traces/cables.

But any problem that you see after a rising edge, but not after a falling edge, is caused by the DAC. In this case, the voltage sags because the DAC's output amplifier is not strong enough to quickly handle the change in the load. (This amplifier is specified as having a slew rate of 0.55 V/µs and a short-circuit current of 15 mA. In contrast, the GND line is able to quickly sink much more current.)

You can reduce this problem by buffering the DAC_IN signal with a faster and stronger opamp.


While it's not directly the issue here, you're misinterpreting the specifications of the analog switch.

The analog bandwidth of an analog switch refers to the highest frequency that can pass through the switch without attenuation by more than 3 dB. It does not refer to the rate at which the switch turns on and off in response to the control signal. That specification is not actually specified in the 74LVC1G137 datasheet, but the most relevant ones that are specified are ten and tdis, which are respectively the time between S going high and B2 being connected to A and the time between S going low and B2 being disconnected from A.

The actual rise and fall times of the output are not specified.


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