# Capacitances for inverter delay calculations

In CMOS VLSI DESIGN, Neil WESTE, page 144.
"The source-to-body capacitors Csbn1 and Csbp1 have both terminals tied to constant voltages and thus do not contribute to the switching capacitance. It is also irrelevant whether the second terminal of each capacitor connects to ground or power because both are constant supplies, so for the sake of simplicity, we can draw all of the capacitors as if they are connected to ground."

I have several questions:

1. I don't understand why Csbn1 and Csbp1 do not contribute to the switching capacitance (yes but why constant voltages are significant there).
2. Then, "irrelevant whether the second terminal of each capacitor connects to ground or power because both are constant supplies' ', I also don't understand why the second terminal is not irrelevant.
3. Finally, the actor said: "draw all of the capacitors as if they are connected to ground".
4. Why Cout = Cdbn1 + Cdpp1 (meanwhile they are not parallel) + Cwire + Cgsn2 + Cgsp2 (also not parallel).
5. Where is Cgb (gate-body) in his explanation ?

I'm sorry, but I really don't understand. I hope someone will explain for me in more details.

I don't understand why Csbn1 and Csbp1 do not contribute to the switching capacitance (yes but why constant voltages are significant there).

Both source and bulk are connected to constant voltages. E.g. for the n channel FETs Source is on GND level and the bulk is connected to the substrate which is usually tapped somewhere to the GND potential as well. The assumtion is, that these two "nets" are connected well enough that there is no dynamic voltage change across the source-bulk capacitance and therefore no current. Keep in mind that if your source and bulk connections are not close to each other, this assumption might be wrong and the capacitance needs to be accounted for.

Then, "irrelevant whether the second terminal of each capacitor connects to ground or power because both are constant supplies' ', I also don't understand why the second terminal is not irrelevant.

Have a look on how AC analysis is performed on a network (shorting the DC voltage sources, effectively making VDD and VSS the same net for small signal analysis). In fact you can swap any capacitance terminal connected to a constant voltage to any other constant voltage net. Constant voltages take no part in the solution for AC voltages and currents.

Finally, the actor said: "draw all of the capacitors as if they are connected to ground".

In theory you could connect all of them to VDD. Does not make a difference (the VDD power supply is a short for small signal analysis). So VDD, GND and all other DC voltages are the same. The convention is to use GND as it serves as reference potential GND = 0V by definition.

Why Cout = Cdbn1 + Cdpp1 (meanwhile they are not parallel) + Cwire + Cgsn2 + Cgsp2 (also not parallel).

Cdbn1 is between the output node and the bulk of the NFET, which is the same as the source, which is the same as the negative supply (GND). Cdpp1 is between the output node and the bulk of the PFET which is the same potential as the source of the PFET which is the VDD potential.

From an AC perspective VDD and GND are the same net, as they are connected together with a low impedance DC voltage source and therefore can be shorted for AC analysis.

This leads to the fact that both capacitances act the same way as if they both were connected to GND.

Where is Cgb (gate-body) in his explanation ?

Either ignored or added to the Gate-Source capacitance (as bulk and source are the same net according to the above assumtions).

Note that all of these assumtions and techniques only reflect the reality, if the DC power supply's impedance is indeed as close to a short as possible (block caps between VDD and VSS help reducing this impedance). If there is a significant source resistance, this way of analyzing the circuit does not provide accurate results.