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In SystemVerilog and in VHDL as well, we can parameterize the length of ports on modules/entities. This means that the bit length of a port can be changed by using a parameter/generic. The required parameter/generic is specified when the module is instantiated.

Is it possible to take a parameter value and pass it to a function that will then return a value that is then used to do the actual parameterization? This could be done explicitly or implicitly.

// Explicit way
register #( .WIDTH(MyFunc(64)) ) D_rg
(
    .clk(clk),
    .rst(rst),
    .wen(1'b1),
    .D(data_in),
    .Q()
);

// Implicit way - this shall call the MyFunc internally on WIDTH parameter
register #( .WIDTH(64) ) D_rg
(
    .clk(clk),
    .rst(rst),
    .wen(1'b1),
    .D(data_in),
    .Q()
);

I believe that the explicit method should be possible, but I am not sure about the implicit method.

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1 Answer 1

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You can set a parameter by calling a constant function. Refer to IEEE Std 1800-2017, section 13.4.3 Constant functions. There is a long list of restrictions for a function to be considered constant.

This is legal if MyFunc is a constant function:

register #( .WIDTH(MyFunc(64)) ) D_rg

Verilog can not call function MyFunc internally or implicitly with this code:

register #( .WIDTH(64) ) D_rg
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