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I am trying to understand how much propagation delay of the clock signal is allowed between two AD7984 as described in AD7984 "Chain mode without busy indicator" on page 22.

This is how I understand the timing:
On the falling clock edge, device A holds its SDO level for another \$t_{HSDO}\$ (min. 3ns). This level is seen by device B input, so at same time, SDI of device B feeds its internal shift register. In order to do that, the input has to fulfill the Setup \$t_{SSDISCK}\$ (min. 2ns) and Hold \$t_{HSDISCK}\$ (min. 3ns) time.

So the SDO level of device A holds for min. 3ns after falling edge and the min hold time for device B SDI is 3ns. 3ns-3ns=0ns -> So I have no margin there if the clock has a propagation delay of 1ns for example, right?

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I agree, it sounds like this part is designed right at the limits, and the datasheet makes reference to the hold time already (extracts below). But as it's a key feature, I'd expect / hope that this part is designed and tested to work correctly in a chain.

So I have no margin there if the clock has a propagation delay of 1ns for example, right?

True... but, don't forget that the data needs time to propagate too - so unless your clock is taking a very circuitous route, the two signals should arrive at similar times. Your routing can also skew the sample point of each ADC, as shown below.

I was a little surprised not to find something about this in the Layout section of the Application Hints (page 24), but see below for further clarification regarding the layout.

In addition to this, don't forget that 1ns is ~150mm - so you have to introduce quite a significant discrepancy in the lengths before you see a whole nanosecond - you're more likely to see tens to hundreds of picoseconds without much effort.

"With the Flow" Routing

The data travels alongside / with the clock, so any propagation delays will be "cancelled out".

example of good routing

"Against the Flow" Routing

The data travels against the clock, meaning that the last ADC in the chain gets the clock a little bit earlier than the one before, giving it a small advantage from the hold time point of view. If your host is sampling on the falling edge too, then this is also likely beneficial there as well.

example of "bad" routing


"The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. [...] The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate and consequently more AD7984s in the chain, provided the digital host has an acceptable hold time." (page 22, emphasis mine)

timing diagram

timing specs for SCK falling to data change

timing specs for setup/hold around SCK falling

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  • \$\begingroup\$ Thank you. I already tested with a 12cm/8xADC chain and it was okay. Now I have 16 ADC-chain, but the simulated signal integrity of my clock is bad, so i splitted the clock into clock_A and clock_B with 2 buffers (the SDO-SDI chain is the same with 16 ADCs) My clock buffer has 1ns skew between the outputs, so this could be enough to bring the chain into trouble. Question to your routing hint: I thought it is better to route against the flow: if my SDI hold time is 3ns and the clock reaches the SDO 100ps later, then I have a effective t_HSDO of 3ns + 100ps. Thats larger than t_HSDISCK \$\endgroup\$
    – cyrus010
    Commented Dec 8, 2023 at 16:31
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    \$\begingroup\$ "I thought it is better to route against the flow" ... On reflection, I think you're right with that one! My apologies, I'll reword it. \$\endgroup\$
    – Attie
    Commented Dec 8, 2023 at 17:21
  • \$\begingroup\$ Re signal integrity - what speed is your clock, and do you have lots of stubs in the path? If you can keep the stubs short, then I'd be surprised if you need any buffers - termination may help too. \$\endgroup\$
    – Attie
    Commented Dec 8, 2023 at 17:28
  • \$\begingroup\$ I had a single 320mm long 50Ohm CLK with 16 short (1-2mm) stubs and series-termination. A thevenin termination helped, but my driver was to weak for that. Now I figured out that I can make 2 paths with the same lenght (aprox 140mm each) and place a series termination at the beginning of each path. So I could split: 8 ADCs in one path and 8 ADCs in another path, all with the same driver. Looks also good in simulation. \$\endgroup\$
    – cyrus010
    Commented Dec 8, 2023 at 17:36

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