In a discussion on multiplier circuits, my textbook (Brown and Vranesic's Fundamentals of Digital Logic, 3e) write that
When a shifted version of the multiplicand is added to a partial product, overflow has to be avoided. Hence the new partial product must be larger by one extra bit. Figure 3.36a illustrates the process of multiplying two positive numbers. The sign-extended bits are shown in pink. Part (b) of the figure involves a negative multiplicand. Note that the resulting product has 2n bits in both cases.
I have supplied Figure 3.36 below.
I am confused about two things:
(1) Why are the pink sign extensions necessary at all (I think this has to do with the overflow discussion above but I can't quite understand why). In particular, I see no issue with simply adding \$PP_n\$ to \$M_{n+1}\$ in order to generate \$PP_{n+1}\$, while allowing \$PP_{n+1}\$ to be one bit longer than each of the inputs to that adder row so that any carry-out is stil accounted for. Why then do we still do sign extension?
(2) Why does the very first partial product have two bits of extension?
A very nice answer below sees to suggest that the issue is that without sign extension, the "extra bit" that I suggested keeping can be wrong. In the below, the extra 0 bit is wrong.
Partial product 1 101011
+ 00000↓
-------
010101
One might ask why can't we just delete the extra bit if it might be wrong: after all, in the above we would get the correct 10101 output under this strategy. But of course that won't work in general (we know this on the general grounds that we need an n+1 bits to account for the addition of two n-bit numbers) and also by explicit example:
Partial product 1 101011
+ 10000↓
-------
100101
Here ignoring the carry out of the final stage gives us the wrong answer again, 00101. Thus neither keeping nor excluding the final bit gives us the right answer in general. Only sign extension gives us the right answer in general.
See also my question here which I think bears on this.