How do wires behave in testbench file in Verilog?

Question

I am a beginner in Verilog, and when I study the testbench file, I am very confused about how the wires behave between the submodules in the file.

The testbench file:

module testBench;
  wire w1, w2, w3, w4, w5;
  binaryToESeg d (w1, w2, w3, w4, w5);
  test_bToESeg t (w1, w2, w3, w4, w5);
endmodule

module binaryToESeg
  (input A, B, C, D,
   output eSeg);
  nand #1
    g1 (p1, C, ~D),
    g2 (p2, A, B),
    g3 (p3, ~B, ~D),
    g4 (p4, A, C),
    g5 (eSeg, p1, p2, p3, p4);
endmodule

module test_bToESeg
  (output reg A, B, C, D,
   input eSeg);
  initial // two slashes introduce a single line comment
    begin
    $monitor($time,,
      "A = %b B = %b C = %b D = %b, eSeg = %b",
      A, B, C, D, eSeg);
    //waveform for simulating the nand ftip ftop
    #10 A = 0; B = 0; C = 0; D = 0;
    #10 D = 1;
    #10 C = 1; D = 0;
    #10 $finish;
  end
endmodule

The image provided by the book:

Above is the image provided by the book illustrating the interconnection of Design and Test modules. However, from the code to instantiate the two modules named d and t, I find that there is no reason for w2 to connect port A between these two modules.

Besides, why is the w2 pointed to the right instead of pointing to the left and w1 pointing to the left instead of pointing to the right? How can I define the direction of w2 and the remaining wires?

I think the Verilog code here adheres to IEEE Std. 1364-2001.

Answer 1

Wires are simply just connections between. They have no specific direction.

You have a module binaryToESeg which declares four inputs, A,B,C,D, and one output eSeg.

You have a second module test_bToESeg which declares four outputs, A,B,C,D, and one input eSeg.

You then have a top level module testBench which connects the two modules together. The image shows a simplified "black-box" view of the system, showing what signals are connected between the two modules, and the direction the signals flow (output to input).

For the sake of clarity, I have rewritten the testbench below using explicit port connection (you really should always use the explicit syntax, for clarity and easier verification):

module testBench;
  wire w1, w2, w3, w4, w5;
  binaryToESeg d (.A(w1), .B(w2), .C(w3), .D(w4), .eSeg(w5));
  test_bToESeg t (.A(w1), .B(w2), .C(w3), .D(w4), .eSeg(w5));
endmodule

Hopefully with the testbench rewritten, it becomes clearer what is happening. The wires simply connect between the two modules, feeding signals from the output of one module, to the input of the other module, and vice versa. The wire itself doesn't have a direction, it is set by the port of the module.

Syntactically, there would be nothing to stop you using a wire to connect just two inputs together, or just two outputs together, but the result would be warnings/errors from the synthesis tool about a net having either no drivers or multiple drivers.