Sorry in advance for a long question. I'm working on designing some pre-amplifiers to amplify signals from a Multi-Wire Proportional Chamber for a nuclear physics experiment. Each signal from these wire chambers is basically a current pulse that deposits a total charge on the order of 10 femtoCoulomb over the span of 10-100ns or so.
The design will be implemented with SMD components on a 6-layer PCB and the trace height above a ground plane will be about 0.08 mm. This is because the pre-amplifiers will be spaced very close to one another, and we want to minimize cross-talk.
We want pulse heights to be proportional to charge deposited and each pulse should decay before the next pulse arrives, so from this I understand that the topology should be some kind of lossy integrator/charge amplifier.
A typical charge amplifier that I've seen all over is roughly this topology. V1, I1, R1, and C1 model the MWPC itself, as the wires are kept at high voltage through a pull-up resistor, and a high voltage decoupling capacitor is needed to protect the amplifier electronics. Let's call this one design 1:
As I understand it, this charge amplifier topology effectively eliminates the effects of any R4/C2 because of the virtual ground at the negative input terminal, which is beneficial if C2 is not well-known, such as for a long cable. However, this is not a concern for my application, as the pre-amplifiers are onboard the MWPC detector itself. A rough calculation with a microstrip capacitance calculator gave me about 1 pF of shunt capacitance for the traces of my input line.
However, the capacitor C3 alone sets the charge-to-voltage gain of the integrator, and for something like 10 fC of charge, even a 4 pF capacitance only gives 2.5 mV. It would be nice to have a larger signal, but I am concerned that making the capacitor even smaller than that would mean that parasitic capacitances could heavily change the gain and response of the circuit.
The pre-amplifiers are onboard the PCB of the detector itself, to minimize noise before the signal is amplified, so space limitations make it difficult to fit a second stage of amplification after the first stage. I came up with an inverting and a non-inverting alternative design below.
For the non-inverting amplifier (design 2), C2 would be about ~4 pF (total including the ~1 pF shunt capacitance of the trace) and R1 would be chosen to set the decay time constant, while R4 and R3 would set the extra gain that I was hoping for. C3 is there to account for input offset voltage, and would be large.
For the inverting amplifier (design 3), C5 would be ~4 pF similarly, but R10 would set the decay time constant through the virtual ground and the R11/R10 ratio would give the extra gain.
My main question is: I see that design 1 is often used for this kind of detector, whereas I haven't seen any topologies like designs 2 or 3 used. It seems that designs 2 or 3 can provide better gain without an extra stage. Design 1 can eliminate the effect of the input capacitance, but this seems to be a much more minor concern here, since the amplifiers are onboard, without any long cable connecting them. Am I missing some critical flaw that makes designs 2 or 3 inappropriate for this application, or a significant other benefit of design 1?
One potential issue might be stability. Since the positive input on the inverting design is grounded, design 3 should have only negative feedback and so be stable.
Design 2 doesn't have a grounded positive input, and so a sufficient amount of capacitive coupling between output and input would cause oscillation. Experimenting with this in simulation gives around 0.1 or 1 pF where this starts to become an issue, for a R3/R4 gain of 100 or 10, respectively. However, on the PCB layout I've prepared for design 2, the traces seem to be far enough away from each other to keep the capacitance between them well below this. And in the worst case, I can simply lower the resistor gain to reduce the loop gain and still end up with a higher gain than design 1.
So overall, I'm just trying to find out if there's anything I've missed that can be spotted straight from the topology and design specs, or if I just need to bite the bullet and print design 2 or 3 and see if it works or not.
