On previous PCBs I've laid out, I've always been able to place decoupling capacitors easily due to VDD/VSS pairs being close together. However, I'm now working on a design that's using a chip (ISSI IS45S32800J SDRAM) which has its power supply pins spaced out on opposite sides of the chip:

chip pinout

I'm using a 4-layer PCB and was planning to just put all the decoupling caps on the bottom layer for convenience, but knowing that the caps should be placed as close as possible to the chip pins, the required traces (putting the caps in the middle between both pins) seem way too long.

How is decoupling such a chip usually handled? Am I overthinking things?

  • 2
    \$\begingroup\$ "Am I overthinking things?" Yeah probably. What does the datasheet or application notes say? \$\endgroup\$
    – user319168
    Commented Dec 11, 2023 at 23:58
  • \$\begingroup\$ The datasheet seems to have zero recommendations regarding PCB layout. I went on to the manufacturer website but it just seems to offer the same basic datasheet I already have \$\endgroup\$
    – Triforcer
    Commented Dec 12, 2023 at 0:01
  • 1
    \$\begingroup\$ They're only 1 cm apart across the top and bottom of the chip. That is relatively close by the standards of the relatively low frequency SD ram. Consider that if you put the capacitor on the back side of a 1.6 mm board you would have 1/3 of that distance just passing through the board thickness before you have any lateral distance. \$\endgroup\$ Commented Dec 12, 2023 at 0:03
  • \$\begingroup\$ @user1850479 That's a good point, thank you \$\endgroup\$
    – Triforcer
    Commented Dec 12, 2023 at 0:08
  • \$\begingroup\$ Putting the capacitors on the opposite side of the board seems like a good way to position them pretty close to the pins. \$\endgroup\$
    – Hearth
    Commented Dec 12, 2023 at 0:10

3 Answers 3


The inductance to the caps is what is important, not the physical distance.

With 4 layers, you will have a ground plane, and probably a power plane also.

Planes have very low inductance, so you want to get the cap traces to the planes with short traces.

Wider traces have lower inductance, so make your traces as wide as practical.

If you have a solid power plane, connect the cap to the power plane with a short trace.

If you don't have a power plane, or it is lousy, put the cap close to the power pin as shown below.

enter image description here


Use single or double vias for each pin, and place the decoupling caps nearby. Use an inner plane VCC/GND pair. This serves as a practically ideal connection between vias into the plane pair, greatly relaxing the pressure on placing bypass caps.

Where you have space, then, bypass caps can be put near pins, and where routing congestion is tighter, just get them close enough. You might not even need one cap per pin pair, or however many caps per chip (i.e. sharing caps between nearby chips).

By multiple vias, I mean somewhat like this:

enter image description here

From: Via layout for decoupling capacitors

but with appropriately sized vias, shorter spacing, and inner planes of course.

See also: How to minimize impedance from capacitor to Gnd and Power planes

Another excellent answer here: https://electronics.stackexchange.com/a/74572/311631 Ultimately what you're doing is constructing a power distribution network (PDN) and getting a consistent low impedance to each pin/pair.

SDRAM isn't too picky. It's old technology; it can even be done on two layers, if you have the space to route it carefully. You need to keep solid ground around it, it's very easy to lose signal quality or EMC this way, and I certainly don't recommend it generally speaking; but just to say -- it's possible.


The answer here is to remember the function of the pins. The pins near the center of the device are all inputs. They aren't driving a signal back to the controller and as such don't need a decoupling cap to handle the io driver switching currents. Instead you just need caps to manage the internal ic switching and return back to the controller driver.

The same for the corner vdd and vss pins. They are providing power and return for the internal logic. For all vdd and vss pins you should place a cap at each pin. You could place one underneath but personally I would not share the cap but instead put one by the vdd pin and another by the vss pin and so on. You can then keep traces to vias and to planes short.

The vddq and vssq pins are your data io driver power pins. These need to provide a low impedance path for the power to the data drivers, driving back to the host.

You will note that there are two vssq and two vddq pins on each side.

Here you should place the caps between each vddq /vssq pair. To avoid interfering with the dq fan out, you could place the caps underneath the sdram, and place vias at the pins, straight down to the caps, tied to the respective vddq and vss (gnd) plane.

I would use 16 caps. You could get away with 12 if you share one between each vdd/vss pair. Optimal placement for caps would be top side, next to the sdram. If space is tight, then place on the rear under the parts pins, especially if it is a 1.6mm board.


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