This is regarding a design choice involving LAN8720, specific to clocking schemes.

We are interfacing an ARM cortex M4 (with inbuilt MAC) to the 8720 PHY via RMII in the REFCLKO configuration. In the datasheet for the 8720, Fig 3.9/page 36 (sorry but i do not have enough points to upload an image) shows the 8720 receiving its clock from an external source(25 Mhz) and the MAC is fed an output reference clock of 50MHz from the 8720. The text in the datasheet prior to this figure reads: *"In some system architectures, a 25MHz clock source is available. The device can be used to generate the REF_CLK to the MAC as shown in Figure 3.9. It is important to note that in this specific example, only a 25MHz clock can be used (clock cannot be 50MHz). Similar to the 25MHz crystal mode, the nINT function is disabled."* Absolutely nothing else on this scheme is mentioned.

Now, the controller itself is clocked by a 25MHz crystal. The controller generates a 25MHz signal on its MCO. From the figure mentioned above, it should be a correct design to clock the 8720 via the MCO output of 25MHz from the controller and providing the REF_CLK output to the controller's MAC. However as mentioned earlier there is hardly any information(read none) regarding this. There are development boards of 8720 which support every other clocking scheme but this. I even checked the schematic review checklist provided by SMSC which describes quite a few clocking schemes but doesnt mention this at all. Are there any issues known with such a clocking scheme?

See the third document in the link below. http://www.smsc.com/Products/Ethernet_and_Embedded_Networking/Ethernet_Transceivers/LAN8710A_LAN8720A/Download (As mentioned earlier, I do not have enough points to upload an image)


1 Answer 1


Circuits depicted by figures 3.8 & 3.9 actually work the same way, from the MAC's point of view. The only difference between them is the way the clock signal is generated for the PHY: 3.8 uses the internal crystal oscillator, 3.9 uses an external oscillator. Since 3.8 is demonstrated by the eval board of SMSC, I'd expect 3.9 to work as well.

However, there is a single note in the data sheet that you should pay attention to: "The REF_CLK Out Mode is not part of the RMII Specification. Timing in this mode is not compliant with the RMII specification. To ensure proper system operation, a timing analysis of the MAC and LAN8720 must be performed."

I have never tried to build a circuit with this PHY, so I don't know the exact implications of this note, but I'd expect the problem to lie in the fact that having a common, external oscillator being fed into both the MAC and the PHY can give you a controllable delay between them (you can play with the lengths of the two clock lines), but having the PHY sourcing the clock to the MAC will not give you this freedom, probably limiting the distance between them considerably.

  • \$\begingroup\$ Had not spotted the note at all. Distance limitation is something I anticipate. I guess I'll know when I try it out. I am primarily concerned by the lack of support for this particular clock scheme on any of the eval boards, despite it being mentioned in the datasheet. \$\endgroup\$
    – Rustin
    Oct 22, 2013 at 10:21

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