Why do we alternate directions between metal layers?

Question

In their CMOS VLSI Design and in the context of a discussion about the initial stages of floorplanning/physical design, Weste and Harris write that

Another important decision during floorplanning is to choose the metal orientation. The MIPS floorplan uses horizontal metal1 wires, vertical metal2 wires, and horizontal metal3 wires. Alternating directions between each layer makes it easy to cross wires on different layers.

They seem to answer the question in my title here in their last line, but I'm afraid i don't understand the justification. In particular, why do we want to be able to cross wires on different layers? Is this related to or derivative from some heuristic about how best to get signals from one place to another in a chip?

Answer 1

This is exact same issue as on a 2-sided PCB.

If one side has wiring going only vertically and the other side has wiring going only horizontally, you can draw a signal from any point to any other point as long as you can switch layer to do a 90 degree turn between horizontal and vertical wires.

You can't do that if both two layers only are allowed to draw e.g. horizontal wires, then you can't draw any vertical wires.

And if you allow drawing of both horizontal and vertical wires, or even diagonal or arbitrary wiring on both layers, if you have already one wire going from top left to bottom right either diagonally or just horizontally and vertically with 90 degree angles, you then cannot cross that wire on the same layer any more.

Answer 2

This is primarily for ease and feasibility of routing. If you keep all routes vertical on one layer, all routes horizontal on the next, then you avoid a wide class of situations where you metaphorically paint yourself into a corner.

Nets that need to cross have a clear path to do so, by either a via going up or down to an adjacent perpendicular layer, but more importantly, if you're running a long distance vertically or horizontally, an impassable (perpendicular) obstruction on the same layer is much less likely to be possible. If you have only vertical wires on a layer, you never hit a horizontal obstruction on that layer.

For analog design, the design principle I happened to use was:

• Local routing, short runs in any direction necessary, on M1
• M2 would run horizontally, often carrying gate signals between parallel fingers of a transistor
• M3 would bring in sources/drain signals and connect to M2 to reach gates for feedback/cross-coupling in the same cluster)
• Further layers would provide interconnect between these transistor clusters.

Here's a partially annotated layout showing this in the switching quad of an active mixer:

As described above, M1 is used for local interconnect (poly-M1 vias to the point where they reach their horizontal rails) and odds/ends (connections to the guard rings, dummy transistor routing, etc). M2 carries the gate signals (the IF of my mixer), while M3 brings signals into and out of the cluster.

Outside of the image (above and below), M4 would be used to interconnect same-net M3 lines, although I could have done this interconnection on M2.

The result is as described above - most signals get clear runs for a significant distance, and when they do need to cross, there's a clear path to actually crossing on the next layer. There are no situations where a signal just runs into a dead-end (which would entail doing a lot of rip-up and rerouting).

Note that unlike the topic of your quoted paragraph, which discusses a floorplan for a digital circuit, this is a local slice of an analog circuit. However, the principle still applies.