# Why do we usually operate well into strong inversion?

In textbooks like the venerable Gray and Hurst or in contexts like my introductory analog design class, it was always emphasized that with MOSFETs we always want our designs to obey some constraint like $$\V_{ov} > 150\$$ mV. A somewhat closer analysis of this constraint shows us that this constraint is equivalent to the requirement that we have all transistors in our designs operating well into strong inversion. I have two questions about this:

(1) What is the reason for so stridently wanting to avoid dipping into moderate or even weak inversion with the effect of our small signal on the gate? Given that it's well known that we get more transconductance in weak inversion than in strong inversion, it can't be that the gain is deleterious. Does it have something to do with linearity and distortion of the signal?

(2) What are the main problems with operating in weak inversion more generally? Given that it has higher transconductance, all else equal it seems we would want to operate there. I know some designs do, so I'm wondering what the difficulties are in doing so with all designs. Perhaps Gray and Hurst will answer this later in the text though...

I'm generally a big fan of using weak inversion, owing to the fact that I studied analog design under professors whose backgrounds were power-constrained biosciences and power-constrained RF.

One problem with weak inversion is the poor f_t (transit frequency). For a given power budget and length, weak inversion requires the transistor to be made very wide. As a result, the transconductance may be high, the transconductance efficient per current may be high, but the transconductance per transistor area is poor.

This may or may not be a big issue for you depending on where the other poles are. This wasn't a huge issue for projects related to biosignals (dominant poles were usually associated with some later output stage or a dominant pole compensation), but caused some trouble for the RF related ones.

(1) What is the reason for so stridently wanting to avoid dipping into moderate or even weak inversion with the effect of our small signal on the gate? Given that it's well known that we get more transconductance in weak inversion than in strong inversion, it can't be that the gain is deleterious. Does it have something to do with linearity and distortion of the signal?

Output-referred linearity and distortion (i.e. how large of a swing we can drive into the output) is more a matter of headroom on the drain side of the transistor. If you imagine the simplest case of a common-emitter amplifier with a drain resistor, you get distortion when the transistor enters the triode mode of operation, or when it cuts off entirely. The allowable range of outputs depends mostly on the supply voltage and the inversion coefficient doesn't really matter.

Input-referred distortion (i.e. how large of an input swing is OK) is bound to happen regardless of the inversion coefficient that's being used, unless mitigated with the use of feedback which sets gain and linearizes the system. In this regard, a weak-inversion system with the same current is (superficially) worse just because it has a higher open-loop gain.

However, linear feedback around an amplifier or other structure will take the open loop gain and convert it to a lower-magnitude, more-predictable, and more-linear closed-loop gain. It's the same thing if you're adding feedback to an integrated amplifier in your VLSI design, or an op amp in an audio amplifier.

In practice, the closed-loop gain reflects the actual end-user need of the circuit, and isn't simply maximized. A strong-inversion amplifier with an open-loop gain of 1000 or a weak-inversion amplifier with an open-loop gain of 10000, will both provide around the same gain when using the same feedback network. The higher the open loop gain, the closer the closed loop gain is to the ideal gain set by the feedback.

What are the main problems with operating in weak inversion more generally? Given that it has higher transconductance, all else equal it seems we would want to operate there. I know some designs do, so I'm wondering what the difficulties are in doing so with all designs.

Another issue is that the gain being high isn't always great. A small Vth mismatch (or induced/coupled voltage or whatever) is much more deleterious in situations like current mirrors, where I don't need huge gain so long as both halves are properly matched and interdigitated.

• Beautiful answer, thank you! At this point a few of the arguments are above my pay grade, but hopefully these are things I will eventually get as I read on. Much appreciated!
– EE18
Commented Dec 15, 2023 at 19:23
• @EE18 No problem, very happy to help! Please let me know which arguments I could explain better; I'd be happy to try to elaborate/break them down further, Commented Dec 15, 2023 at 19:25
• Transconductance efficiency per area can be visualized by looking at the product $\frac{g_m}{I_D} \cdot f_t$ plotted vs current density. It peaks around moderate inversion. Commented Dec 15, 2023 at 19:31
• Thank you for offering! Perhaps if you get the chance, an expansion on the middle point regarding linearity would be very helpful for me. In particular, I don't know that I followed your distinction between input- and output-referred distortion (I'm generally familiar with the concepts, but don't see how the consequences you outlined follow).
– EE18
Commented Dec 15, 2023 at 19:51
• @EE18 No problem, I'll try to do so at some point soon Commented Dec 15, 2023 at 19:55

There is nothing wrong with operating in weak inversion, it is just slow.

It is slow from a small-signal and large-signal perspective:

• Small signal bandwidth is dictated by $$\\frac{g_m}{C}\$$. Typical plots of $$\\frac{g_m}{I_D}\$$ have current density plotted on a logarithmic scale for the x-axis. That means current density decreases exponentially as $$\\frac{g_m}{I_D}\$$ increases. Current density is inversely proportional to device size which is directly proportional to $$\C\$$. Long story short, $$\C\$$ grows faster than $$\g_m\$$ and bandwidth is reduced. You can see this by plotting $$\\frac{g_m}{I_D}\$$ and $$\f_t\$$ on the same x-axis.
• Large signal bandwidth is dictated by the slew rate. Slew rate is equal to $$\(\frac{g_m}{I_D})^{-1}\$$. Weak inversion has large $$\\frac{g_m}{I_D}\$$ and low slew rate.
• Just to make sure I'm following your chain of proportionalities argument, you are saying that increasing $g_m/I_D$ results in an exponential increase in $C$ throughout the MOSFET structure?
– EE18
Commented Dec 15, 2023 at 19:56
• I am not saying that a linear increase in $g_m/I_D$ corresponds to an exponential increase in $C$—the $g_m/I_D$ curve is pretty non-linear. I am saying that since the x-axis is typically $\log(I_D/W)$, whatever the $g_m/I_D$ curve is, capacitance is increasing exponentially as you go left on the x-axis. Commented Dec 15, 2023 at 20:26
• Regarding the relationship between $C$ and $W$, most capacitances are proportional to $W$, so as $W$ increases exponentially we can expect $C$ to increase exponentially as well. Commented Dec 15, 2023 at 20:28

What is the reason for so stridently wanting to avoid dipping into moderate or even weak inversion with the effect of our small signal on the gate?

We need a lot of electrons below the Oxyde to convert the p-type Silicon into an n-type one. We don't want the 2D electron gas recombine with the holes.

Given that it's well known that we get more transconductance in weak inversion than in strong inversion

To confirm that sub-threshold MOSFET's technology is emerging for ultra low power products.

Proper mos device modeling in sibthreshold was not available before EKV model. Level3 and bsim2 models both had tens of percent error in gm at threshold. That gave the field a touch of black magic: you n