Justification for equivalent gate capacitance simplification in digital circuits

Question

A MOSFET is, in reality, a four-terminal device with capacitances between each pair of terminals:

These capacitances are, of course, the standard MOSFET intrinsic and extrinsic differential capacitances (i.e. they are defined as \$C = dQ/dV \$ where \$Q\$ is the charge on one of the terminals and \$V\$ is the voltage difference between said terminal and the other terminal).

That being said, it is well known that when we do digital design, we sweep a lot of this under the rug. Indeed, in their CMOS VLSI Design, Weste and Harris claim that

(1) It is convenient to view the gate capacitance as a single-terminal capacitor attached to the gate (with the other side not switching [this is in turn equivalent to saying that the capacitance's other node is ground, as discussed here]). (2) Because the source and drain actually form second terminals, the effective gate capacitance varies with the switching activity of the source and drain. Figure 2.11 shows the effective gate capacitance in a 0.35 um process for seven different combinations of source and drain behavior [Bailey98].

Figure 2.11 is from the Bailey paper (D. Bailey and B. Benschneider, “Clocking design and analysis for a 600-MHz Alpha microprocessor,” JSSC, vol. 33, no. 11, Nov. 1998, pp. 1627–1633) and is provided below:

Even after reading the Bailey paper and the sources cited therein, I am still not sure I understand the nature of the approximations being made. I think it is fair to say that there are two approximations being made though. I am thus led to the following two questions. As an example to illustrate, I will imagine an inverter switching to 0 on its input (1 on its output, though this isn't relevant for the question on the gate here) and focus on the NMOS transistor therein.

(1) The first approximation, I believe, is that with respect to the Gate node (i.e. if there is some circuit driving this node) then we can delete the capacitances \$C_{gs}, C_{gd}\$ and then there is some equivalent capacitance \$C_g\$ which we can put between the Gate node and ground such that, for a given stimulus from the driving circuit to our inverter, the delay until the Gate node charges and discharges is the same as it otherwise would be if we hadn't made this approximation. My question is whether this understanding is correct (i.e. is it the correct understanding of Weste and Harris's comment I have labelled (1) above) and, if so, how we justify this? Also, is it fair to say that this "equivalence" is only in the sense of producing the correct delay for the Gate, but not that it will have the exact same temporal dynamics (e.g. the rise time may differ even if the delay is the same).

(2) The second approximation, I believe, is that we can use the MOS differential capacitances to determine this delay. Given that the relevant charge-storage elements are nonlinear, I suppose a strictly rigorous argument for the time it would take to discharge the gate is the time \$t_d\$ at

$$I_{out}(V_g(t)) = \frac{dQ_{gs}(V_{gs}(t))}{dt} + \frac{dQ_{gd}(V_{gd}(t))}{dt} = \frac{dQ_{gs}}{dV_{gs}}\frac{dV_{gs}}{dt} + \frac{dQ_{gd}}{dV_{gd}}\frac{dV_{gd}}{dt}$$ $$ \equiv C_{gs}\frac{dV_{gs}}{dt} + C_{gd}\frac{dV_{gd}}{dt}$$ where \$I_{out}\$ would is some function of the gate voltage on our inverter depending on the nature of the PDN in the driving circuit. We see that we have reduced the problem to the form involving these nonlinear differential capacitances. This is a differential equation for \$V_g\$ (uncoupled if \$V_s,V_d\$ are constant, though that wouldn't be the case in our inverter. The "data-dependence" noted in Fig 2.11 comes, I assume, from the dependence on \$V_s\$ and \$V_d\$?). Is this basically how one uses the nonlinear differential capacitances of a MOSFET to calculate delay and other times of interest?

If there are any sources that really carefully analyze the approximations which get made here, it would be more than enough to point me to that. Sorry if this question is unfocused. I've tried to spend a lot of time thinking about it but there really does seem to be a lot going on with device modelling here, and in digital design texts it's really swept under the rug. In the end I'm just looking to understand "in principle" what's going on. Thank you!

Answer 1

I can take a stab at trying to answer your question. In both digital and analog design it is helpful/often necessary to have a model of the load that any stage is driving. If the load is a linear network, this load can be replaced by an equivalent driving point impedance that the load presents-- the current and voltage relationship at the terminals of the load (Thevenin equivalent).

In the case of digital gates, we would like to model our loading gates with some equivalent impedance that will give the designer a sense of what kind of load the driving gate is being presented. To be useful in a design context, we would like this impedance to be as simple as possible, and usually abstract it into a lumped capacitance to ground. This lumped capacitor to ground is meant to mimic the I-V characteristic that the actual loading gates would present.

From a network theory perspective, the Thevenin equivalent is only applicable if the network we are deriving an equivalent for is linear and interacts with the rest of network exclusively through two terminals. It's equivalence comes from the fact that as long as we maintain the same I-V relationship at those two terminals, the rest of the network "doesn't know" that we have changed anything. This is what we are attempting to do with our lumped capacitor to ground. We are trying to present a load to our driving gate that will mimic the same I-V relationship as the actual loading gates.

The issue is two-fold. First, our network of loading gates is extremely non-linear. The MOS transistors we are using are intentionally driven into the nonlinear regime to provide the "digital" behavior that we want. Second, even if our load network was linear, if our load network contains more than one reactive element (assuming that the initial conditions can be set independently/ more than one pole) then we can not abstract it away into a single lumped capacitor--- we would require a higher-order impedance. Both of these clash with our desire for a tractable load impedance for first-pass design/analysis.

The solution, as you have seen, is to to try and create a lumped capacitance that mimics the loading gates, in the sense that we try and create a lumped capacitance that will present the same I-V relationship to our driving gates that the loading gates would have. Fig 2.11 is showing how the equivalent lumped capacitance to ground from a MOS gate varies significantly depending on the transitions at the other terminals. Intuitively this is because the voltages across the terminal capacitors are different in the different scenarios (in response to the same gate voltage), resulting in different currents, and hence different equivalent capacitances. The approximation being made is that we view the I-V characteristic that the loading gate presents for a given set of drive and transitions internal to the loading gate, and mimic that I-V characteristic with an equivalent capacitor. If we wanted to design conservatively, we could take the worst case scenario, or we could intelligently choose the lumped capacitance based on what transitions we expect at that gate. You cannot, however, completely/accurately describe the dynamics of the loading network with just one capacitor, since the I-V characteristic that the loading gates present is not a linear function, unlike a capacitor which has a linear Q-V characteristic. In essence the lumped capacitor is a compromise we make as designers to make the design process tractable, but we must always keep in mind that it is merely a model that if used incorrectly can lead to erroneous results.