2
\$\begingroup\$

I've designed a counter using three J-K flip flops, but I have two redundant states. How can I ensure that the system has a way to escape these states if they occur?

I've tried searching for help on the internet, but all of the results I found either skipped around the topic or didn't use J-K FFs.

The states being counted through are 000, 001, 010, 100, 101, 111 (first digit = A, second = B, third = C).

The circuit is:

Ps, please ignore the AND gate leading to Z.

\$\endgroup\$
4
  • \$\begingroup\$ Can you show us the design? \$\endgroup\$
    – Andy aka
    May 16, 2013 at 9:33
  • \$\begingroup\$ I've added a link to it \$\endgroup\$
    – Kadin
    May 16, 2013 at 9:43
  • \$\begingroup\$ So you don't want 011 and 110? Make sure they don't transition to eachother - just map them to one of the valid states. \$\endgroup\$
    – JustJeff
    May 16, 2013 at 10:45
  • \$\begingroup\$ Please add the Karnaugh map you used to determine the logic and the state diagram. \$\endgroup\$
    – jippie
    May 16, 2013 at 18:30

1 Answer 1

Reset to default
2
\$\begingroup\$

It's very likely that the unused states transition within one clock to a valid state; you should check this, but it looks like it to me.

In general, to make sure you get the behavior you want, you should include the unused states in the state diagram up front, and design the system so that they eventually lead to valid states under all circumstances.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.