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I am looking at an open-source design for an NVIDIA Jetson Nano carrier board made by a company called AntMicro. See here The design is an 8-layer design with the following Stack-Up and Build-Up recommendation:

enter image description here

And the Stack-Up:

  • L1: Signal (Top Layer)
  • L2: 5V Power Plane
  • L3: Signal
  • L4: Signal
  • L5: GND Plane
  • L6: 3V3 + Signal
  • L7: GND Plane
  • L8: Signal (Bottom Layer)

The only problem with using this design for my custom carrier board are the capabilities of my manufacturer, which in my case, is JLCPCB.

enter image description here

In the case of the open-source carrier board, inner copper layers are 0.035mm (~1oz) and the outer copper layers are 0.018mm (~0.5oz).

What alternative PCB Build-Up can I use to be able to manufacture the board. Ideally, I do not want to change too much of the routing and layout to be on the safest side.

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    \$\begingroup\$ You're probably better off asking on the projects GitHub page. Given this is a high-speed design with a lot of high speed (multi-gigabit) interface, there is a lot more to consider than just the copper thickness. The dielectric and prepreg (pp) material types used, core/pp thicknesses etc. All of these parameters make a difference to the board routing (impedance matching, trace widths, etc). \$\endgroup\$ Dec 18, 2023 at 13:41
  • \$\begingroup\$ Looking at the JLCPCB page, I don't think they can do that dielectric stack up, so probably you need to make changes to the board or else find a different manufacturer. \$\endgroup\$ Dec 18, 2023 at 15:24

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The 18μm outer thickness is almost certainly the thickness of the un-plated copper foil (not the "Finished thickness" you've shown in the screenshot of JLCPCB's capabilities)... it'll likely be plated up to approx 1oz / 0.035μm (but this isn't actually specified anywhere in the project), and then plated again with a very thin layer of gold (ENIG, as mentioned in the board layout, just below the table you quoted).

Just below the table is also mention of the suggested material - "ISOLA PR2116", which is likely what the project has used to verify the design - so, I'd suggest you either accept their "Advanced PCB" service (6+ layers, but with incorrect layer heights), or look for an alternate supplier.

As always, impedance controlled traces will need to be reviewed if you want confidence that things will work on a new material and stackup.

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    \$\begingroup\$ JLC do actual do a 2116 stackup. You have to select "Impedance Control" to "Yes" and then it gives a list of their standard stackups, but ultimately the thicknesses of each core/prepreg are not exactly the same, so your point still stands (choose a more specialist supplier who can do custom or change the design to suit). \$\endgroup\$ Dec 18, 2023 at 16:14
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    \$\begingroup\$ @TomCarpenter - so they do! I missed that earlier, thanks for pointing it out. \$\endgroup\$
    – Attie
    Dec 18, 2023 at 22:00
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It's unlikely that the board actually has 18 um finished thickness on outer layers. This simply not manufacturable at most fabs because you start with at least 9 um copper foil and plating the vias adds at least 18 um to the outer layers.

It's more likely they're specifying the copper foil thickness and not accounting for plating. The 1 oz finished thickness specified by JLPCB is going to be essentially the same.

That said, if this is a high speed design you should probably do your own impedance calculations too be sure the trace geometry will work with 35 um finished copper.

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