I want to use STM32G031Y8Y6TR WLCSP(1.86x2.14) package, but I have a problem with routing and I'm looking for your advice.

First, I can not use track width less than 0.09mm, also I can not use via less than [0.2mm pad size, 0.15mm hole size] and after routing in KiCad it looks like this. (track width 0.9mm, via size 0.2/0.15 mm)

Kicad editor

As you can see the distance between track and pad is very small and I have to put vias on the pads.
Is it totally wrong or is there any chance to use this package at all?

P.S I manually decreased some pad's clearance to be able to route a track and PCB consists 4 layers.

  • \$\begingroup\$ Why not route the trace from D4 on the layers in between? Are there any obstacles which are not shown in the picture? \$\endgroup\$ Commented Dec 18, 2023 at 15:18
  • 1
    \$\begingroup\$ to properly answer your question we need to know who you are choosing to fabricate this design, because they will have a manufacturability document showing the dimensions to which you can design too. Get the link to that document and share it, then we can move on from there with some faith the design can be produced \$\endgroup\$ Commented Dec 18, 2023 at 15:21
  • \$\begingroup\$ @HansmitmFlammenwerfer So my second question was, Can I use Vias directly on the pads? Seems I can not use TOP(red layer) for inner pads right ? \$\endgroup\$
    – Alatriste
    Commented Dec 18, 2023 at 15:22
  • \$\begingroup\$ @Alatriste It depends on the manufacturing of your vias, maybe you need to adjust the amount of soldermask, since some solder is going down the hole. \$\endgroup\$ Commented Dec 18, 2023 at 15:33

2 Answers 2


Talk to the fab about whether it is possible to route this WLCSP and, if so, their recommendations for how to do it. I suspect you need plated over-filled vias (POFV) to do this. And that is typically a more expensive process. When I last researched using a WLCSP, the added board cost was not worth it for me. Board cost was a bigger concern than size.

JLCPCB does POFV on their advanced PCB process.


A lean way to fan out the inner pins is to use a 4 layer with 0.3mm µ-vias with a 0.1 mm hole and ENIG finish. Officially via-in-pad is required but I would argue that the cavity is only minimal and the risk ok for most applications. Here an example of a 42-WLCSP with 0.4 mm pitch:

42-WLCSP with 0.4 mm pitch. Small holes are 0.1 mm hole µvias while others are 0.2 mm hole through vias

  • \$\begingroup\$ This is interesting for me, in a prototype-ish kind of way. Can you elaborate on how much success you've had with this method, and if you assembled in-house as prototypes (method?) or used an assembly service. Any QA on the results like: imaging, try & die (pry), works/no-works (smokes/ no smokes)? Stencil mods? \$\endgroup\$ Commented Dec 18, 2023 at 21:58
  • \$\begingroup\$ We used it for several prototypes. The last one was delivered as a partial turnkey PCBA. We placed this BGA in-house because the fab did not have it in stock. We either place the BGAs just with Tack Flu or use a stencil + paste. But paste is only required if the BGA has only "half balls". All devices work so far, but they are hardly exposed to temp cycling. Thus pressure built-up in the possible cavitites is of little concern. \$\endgroup\$ Commented Dec 19, 2023 at 10:59

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