I am trying to figure out some basics of digital electronics. We have all seen the squared graph of the computer clock signal:

enter image description here

I have read multiple articles on the Internet and still can't figure out whether the moment of signal value switch (I guess on the graph only approximated as point) is important. It would mean it represents the interval when a circuit gets feeds from the inputs and is expected to propagate the values to the outputs, during the interval and the periods of the stable signal are used for something else?

Or the edges are not important but the periods of the stable signal are and the clock signal could be considered as only one additional circuit input, with high or low voltage set? It would mean the circuit starts e.g. reacting on other inputs when the clock signal is set to 1 and it is expected to get values on the outputs somewhere in that clock cycle - when the clock signal is 1 or 0 right after that?

Only the second option seems logical to me but internet authors regularly write that something is expected to happen on the rising edge, and that a circuit should get its outputs in the interval? That is only a term for saying that signal is set to high now?

If the other option I favour is true look at, for example, a counter register made of a single JK flip flop with its inverted output feeding its J input. It is expected to toggle from 0 to 1 in every cycle. If the circuit should start reacting on its inputs when the clock signal becomes 1, what if the result propagates to the outputs while the clock signal is still 1 and there is enough time to propagate values through the whole circuit once more while the clock signal is still 1 in the same cycle, and toggle the counter once more? I see nothing in the circuit that should stop multiple same-clock-cycle propagations if the circuit is fast enough?


You are right. Edge triggering is just a much narrower form of level triggering, and depends on timing. Inside an edge-triggered device, the changing clock edge is just turned into a pulse which causes it to accept the inputs: a level trigger! But the level trigger is very short. It must be so short that the outputs are not able to propagate back to the input to do any harm in the time that the edge-triggered pulse appears and disappears.

Edge triggering would not work if signals propagated instantly through wires and had unlimited slew rates.

Also note that clocks can be divided into phases to solve problems where this isn't fast enough.

A master-slave flip-flop is an example of clock phasing. It splits the clock signal into two phases by reacting to both rising edges and falling edges, but differently. Input is accepted on a rising edge into an input latch, and then on a falling edge propagated into a second latch where it produces output.

  • \$\begingroup\$ Kaz, your answer at electronics.stackexchange.com/questions/65463/… provided me with almost everything I needed. Great answer, I see that many people visiting hardware forums are not aware of the facts you displayed in the answer, and I couldn't get a clear answer. Thanks \$\endgroup\$ – Срба May 16 '13 at 21:30
  • \$\begingroup\$ Kaz, just take a look at a single JK flip-flop ripple counter link and just the NAND circuit right next to the K input. From the ripple counter diagram I see J and K \$\endgroup\$ – Срба May 17 '13 at 9:50
  • \$\begingroup\$ are always high . So back, to the NAND at K input of a single JK ripple counter: if it is edge-triggered at the moment all the three inputs for the NAND circuit are high and it changes its value to zero. But before zero is propagated to the NAND output the clock (actually output from the field that gets nanosecond high signal for the rising edge) is back to zero, and that nanosecond is shorter then the NAND needs to propagate the values,as you said. Wouldn't it break the expected NAND output (zero)? This nanosecond high signal doesn't do \$\endgroup\$ – Срба May 17 '13 at 9:57
  • \$\begingroup\$ the job in my head at no circumstances. \$\endgroup\$ – Срба May 17 '13 at 9:57

I see nothing in the circuit that should stop multiple same-clock-cycle propagations if the circuit is fast enough?

This is referred to as a hold time violation, and they are terribly fatal to a circuit. It doesn't happen because ASIC creators run expensive timing analysis software to check every single path in the design to make sure that the path is not too fast that the input value could change before the hold time window ends.

Generally paths feed through enough combinatorial cells and the wires have enough RC that the inputs don't change until well after the hold time period expires.

You can read wikipedia about Setup and Hold times for more detailed explanation.

  • \$\begingroup\$ Setup and Hold time violations happen all the time in ASIC's, but when, where, and how they happen are carefully controlled. It is guaranteed to happen whenever there is an asynchronous input. Most reset inputs to chips are async to the local clock, and therefore can have setup/hold violations that need to be addressed in the design. \$\endgroup\$ – user3624 May 16 '13 at 15:20

What's important about a clock signal? All of it, of course! :)

But seriously, there are many aspects to a clock signal and it is difficult to limit it down to just a couple of things. It also greatly depends on what you are doing with it. Below, I will give you some aspects to consider:

Frequency: Some applications require more accurate frequency (and period) than others. An Ethernet interface will require a more accurate clock than something that is controlling a fan. There are many things that can effect frequency, but it is mainly limited to characteristics of the crystal and/or the PLL.

Jitter: I am loosely defining jitter as a change in frequency/period over time. To use old record players as an analogy, jitter is like wow and flutter. Jitter performance is usually not an issue unless you are doing some spread-spectrum-clocking or high speed communications. There is a huge number of things that can effect jitter, including noise, power, the characteristics of any clock buffers, signal routing, signal integrity, and the phase of the moon.

Edges: A good clock edge will rise/fall quickly and monotonically. What I mean by monotonically is that if it is rising then it is only rising (no dips or ringing, etc). If you are feeding a TTL/LVTTL input then we only care about the logic input level thresholds of 0.8v to 2.0v. Between those two levels, the signal should rise/fall quickly and monotonically. Outside of that voltage window, it can bounce around within reason (more on this later). If your edges are not good then you can get double-clocking, excessive jitter, unpredictable timing, etc.

Signal Integrity: Does the signal have a lot of overshoot or undershoot? Is there ringing? While these might not directly effect the usefulness of the clock, it might indicate more serious problems like a badly routed clock trace or improper signal termination. Bad signal integrity also means that you will be radiating and receiving more RF noise than you should-- causing you to fail EMC testing or have a less-than-robust design.

Skew: Clock skew is the difference in clock arrival times at two devices in the circuit. For example, let's say that you have one clock and two devices, but the trace leading to one device is 6 inches longer than the trace to the other device. In that case, the clock skew will be about 1 ns, since signals travel about 6 inches per ns in a wire. Sometimes 1 ns might not be a big deal, but other times it could be a huge deal.

Duty Cycle: Most people think of clocks as being a 50/50 duty cycle, but that is not always true. Many canned oscillators spit out a 60/40 duty cycle, and many chips require a 55/45 (or better) clock input. Buffers, signal routing, edge rates, power, and other factors can also negatively effect the duty cycle. Running clocks as a differential signal can reduce this effect significantly.

So there you go. I hope that helps!


The interval between clocks allows signals to stabilize before the rising edge of the next clock.

Between clock active edges, there may be logic devices that are not clock synchronized and need a few nano-seconds to settle on an output value before the next clock edge arrives on the logic devices that the non-synchronized devices feed.

This is just an example and there are probably better answers to this.

On your JK flip-flop point, if the clock is slow, noisy and/or jittery this may happen but clocks are not meant to be like this.

  • \$\begingroup\$ But look at that JK flip-flop point: as you wrote in the first sentence - the circuit should have values propagated on outputs before the next clock rising edge. In your last sentence you said multiple propagation could occur if the clock is to slow - it means it has to be faster than the propagation - the propagation mustn't occur while the clock is high in that cycle? It leaves me concluding that for every circuit the propagation must occur on the low (zero) signal phase of the same cycle? Am I thinking right? \$\endgroup\$ – Срба May 16 '13 at 13:31
  • \$\begingroup\$ If a clock is slow and there is no noise in the clock or circuitry, at some point the flip-flop output will change state but will not change state again unless there is noise on the clock or jitter. Maybe If I'm misunderstanding your question you should post a drawing of your circuit. You can post to some sites on the internet and provide a link. I or someone else will embed your diagram into your question. \$\endgroup\$ – Andy aka May 16 '13 at 13:36
  • \$\begingroup\$ I have no specific circuit, I was just reading Wikipedia on flip-flops and counters and contemplated on the single JK flip flop ripple counter that is mentioned there but not diagrammed. I will obviously have to read more, e.g. on the terms of noise and jittering that I am not familiar with. It looks that only I have the dilemma on computer clock functioning and the rest of you can easily run a digital circuit with clock in your head and it works for you. Thanks \$\endgroup\$ – Срба May 16 '13 at 14:18

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