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My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the difference between n-well, twin-well, and triple-well processes. My question here is about the reasons why we want to "go up to" triple-well processes (from single-well processes) in the first place.

Weste and Harris make an allusion to the shortcoming of n-well processes by writing the following:

In the n-well process, each group of pMOS transistors in an n-well shares the same body node but is isolated from the bodies of pMOS transistors in different wells. However, all the nMOS transistors on the chip share the same body, which is the substrate. Noise injected into the substrate by digital circuits can disturb sensitive analog or memory circuits.

This leads us to the twin-well process. Weste and Harris write

Twin-well processes accompanied the emergence of n-well processes. A twin-well process allows the optimization of each transistor type.

Questions:

a) This seems to suggest that a twin-well process is advantageous because it allows for the precise doping of the wells (as contrasted with the substrate doping which may vary)? I am suspicious that this is indeed a valid reason seeing as we do a \$V_t\$ implant whether or not we have a well for the given transistor.

b) Is there also an advantage over n-well processes conferred by the isolation associated with a p-well in a p-substrate? That is, by having an independent body node connection to a particular well rather than the whole substrate? Does this sort of pp+ junction even offer isolation of the NMOS body node? I suspect this is more (than a)) the reason for double- and triple-well processes.

c) If b) is true, what further advantage does a triple-well process offer (putting the p-well, in which the nMOS sit, itself in a deep n-well)? Is there even better isolation of the nMOS body node now? Obviously doing this adds capacitance, so do we do this because the pp+ junction of the p-well with p-substrate in a twin-well process does not provide great isolation, as I alluded to in b)?

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    \$\begingroup\$ Twin-well process allows you to bias body of nmos transistors to different voltages than ground (the lowest voltage) in addition to pmos as in n well \$\endgroup\$
    – internet
    Commented Dec 21, 2023 at 3:14

2 Answers 2

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  • Allowing independent optimization of P and N devices is usually not a good enough argument to move from an N-well process to a twin-well process. The reason is that N devices can have near optimal conditions in an N-well process, and they are the fastest devices due to the difference in the mobility factors.
  • A twin-well process could allow manufacturing of both NPN and PNP lateral bipolar devices, and both of them could be better optimized than the single type you could make in a single-well process.
  • A twin-well process could allow independent optimization of P- and N-MOS, however a lightly doped P-substrate is most beneficial for a high speed NMOS which intrinsically is the fastest device due to the mobility factor.
  • A triple-well process allows vertical bipolar devices, which offer some improvements over lateral bipolar devices. The area is typically larger, and they are better isolated against latchup.
  • A triple-well process can help the designer isolate devices from noise in the substrate.
  • The isolation can also be used for enhancing latchup tolerance.
  • A triple-well process allows both NMOS and PMOS devices an isolated body voltage which is important to circuits such as:
    • various bootstrap-switches (important in various high-performance ADCs)
    • some charge-pump and switch-cap circuits
    • HV IO & ESD ? (I am not sure about this one, but since it offers improved isolation it should be relevant to consider)

Notes:

  • This is not an exhaustive answer, I did not spend a lot of time on it. I think the points are true, but please internet, correct my mistakes in the comments or in additional answers if I am mistaken.
  • b) is unclear. NMOS always faster at high currents due to mmobility factor, therefore typically it is a more important device to optimize. And pp+ is not a junction, under reasonable circumstances it is ohmic.
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  • \$\begingroup\$ Thank you very much for your answer. With respect to b), I think it's related to your comment "A triple-well process allows both NMOS and PMOS devices an isolated body voltage". My question in b) is effectively "doesn't the twin-well process also allow for an isolated body voltage in each case"? That is, can't we contact the p-well in the p-substrate and so effectively set that p-well's body voltage. \$\endgroup\$
    – EE18
    Commented Dec 21, 2023 at 13:13
  • \$\begingroup\$ Unless the twin-well process was built on an insulator (I don't assume this as this is normally called silicon on insulator (SOI) en.wikipedia.org/wiki/Silicon_on_insulator ) then no. For example if there is a p-substrate with no insulation to P-wells, then all P-wells must share only 1 potential (Voltage). \$\endgroup\$
    – HKOB
    Commented Dec 21, 2023 at 14:42
  • \$\begingroup\$ And why is that I guess is my question? I am unfamiliar with the isolation properties of a high-low pp+ junction (perhaps there is no isolation?). And if a twin-well process offers no isolation then why is there any advantage over a single well at all? Why not go direct from single-well to triple well? \$\endgroup\$
    – EE18
    Commented Dec 21, 2023 at 15:24
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    \$\begingroup\$ A p-/p+ junction provides no real isolation, other than maybe if the resistivity of the p- substrate is very high. The advantage of a twin tub process is that you can adjust the doping of the P+ regions without having the same doping applied to the N+ regions (which would generally be an undesirable effect, requiring even more N+ doping to counteract). \$\endgroup\$
    – Adam Q
    Commented Dec 25, 2023 at 22:33
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Some of this is answered in Chapter 2.6 of Baker's CMOS Circuit Design, Layout, and Simulation:

a) He argues that a big reason for using twin-well even if you can't isolate the p-wells from one another (each is tied to the p substrate) is so that you can use a very lightly doped p-substrate (so you need more doping, the p-wells, to form transistors) so that your n-wells don't need to compensate so much. This has mobility advantages (compensated semiconductors at the same effective doping level as otherwise uncompensated material have worse mobility because of ionized scattering centers being more present in the former).

b) Per the above, twin-well processes do not really offer p-well isolation (they are all still tied to the substrate).

c) Since b) is false (and as Baker discusses), the triple-well process is what does allow us to vary the well potentials for the p-wells, isolating each from one another.

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