# What is the fastest achievable output speed for an FPGA?

To sum up the question, I would like to know what is the maximum frequency with which I can toggle an output of an FPGA. I do not intend this question to be specific to any particular board or vendor. The following paragraphs briefly describe my setup, and what I have tried so far.

I got an FPGA and a 12 MHz clock source. With no previous experience with such devices, I began searching for Verilog examples and experimenting. So far, I can blink a LED once a second (increment a counter by 358 on every pulse), read button presses (no debouncing yet), and now I am trying different combinations of the two.

I decided to write a small hardware description that would produce exactly 10 pulses when I press the button. Here is what I wrote:

reg led_state;
reg btn_state;
reg [3:0] counter;
always @(posedge clk) begin
if (counter < 4'd10) begin
led_state <= ~led_state;
counter <= counter + led_state;
end
if (~btn && btn_state) begin
counter <= 0;
end
btn_state <= btn;
end
assign led_g = led_state;


I noticed that the code works correctly, producing exactly 10 pulses. However, the frequency of the pulses is 6 MHz (half of the input frequency). I suspect this is because I am using posedge clk, and I was able to get the full 12 MHz out with simply assign led_g = clk;.

To achieve the full speed of the output, I need to run on both posedge clk and negedge clk. So I searched if it's possible to do so, and I found a solution in Verilog:

reg r_clk;
wire xor_clk = r_clk ^ clk;

always @(posedge xor_clk)
r_clk = ~r_clk;


After adding it to my hardware description, I get exactly 10 pulses at exactly 12 MHz. As I understand, it should be possible to multiply the clock signal again to get 24 MHz, then again to get 48 MHz, and so on... What is the trick here? There should definitely be some limitation that would prevent me from doing it, but I don't see it. What is that limitation, and what is the fastest achievable output speed?

• What FPGA are you using? It might have phase-locked loops (PLL) or mixed-mode clock manager (MMCM) resources which can be configured as frequency synthesizers to generate a higher frequency internal clock from a fixed frequency input clock. Dec 20, 2023 at 13:23
• Kind of a broad question. But we're using a Xilinx KU60 FPGA with Xilinx's Aurora serial protocol IP at over 5 Gbps. Dec 20, 2023 at 13:33
• Just a tip, you described that as a 'small program'. It's not a program, it's the definition for some hardware logic. A 'program' mindset will rapidly trip you up when you come to have anything even slightly more complicated. Dec 20, 2023 at 13:34
• @Neil_UK Thanks for the correction. I was also hesitating about this term when writing the question. I understand that Verilog is much closer to PCB schematic than to Assembly, it's just represented in text, not graphically. Dec 20, 2023 at 13:58
• @ChesterGillon I am using GW1NS-2C FPGA. The datasheet specifically mentions "Flexible PLLs" which provide "Frequency adjustment (multiply and division) and phase adjustment" and also "Supports global clock". Dec 20, 2023 at 14:04

The other answer has addressed the xor_clk part of the question.

As for this part of the question:

To sum up the question, I would like to know what is the maximum frequency with which I can toggle an output of an FPGA. I do not intend this question to be specific to any particular board or vendor.

I think that is a broad question for which a frequency can't be given without specific details of the FPGA and board.

Where the maximum frequency of a particular pin can be affected by a combination of:

1. The maximum internal clock frequency of the FPGA.
2. If FPGA pins dedicated for a SERDES are used. Taking the example of Xilinx 7-series devices:
• There a relatively small number of pins dedicated for SERDES which perform serial I/O at GHz frequencies communication such as PCIe v2 operating each lane at 5 GHz.
• Most of the pins support SelectIO which can be configured to support lower frequencies as either single ended or differential (using pairs of pins).
3. The I/O standard of the output.
4. If the I/O standard is single ended or differential. This can impact the board, in needing to use compatible termination resistors and/or trace impedance.
5. The speed grade of the FPGA.
6. The VIO I/O voltage for the I/O bank. This impacts the board design as some FPGAs have multiple banks and different a VIO can be used for each bank. The VIO used for a bank can affect the supported I/O standard.
7. For some Xilinx 7-series devices the FPGA package used, e.g. FF (lidded flip-chip BGA) .vs. FB (lidless flip-chip BGA). See the answer in Cross talk within IC package

The xor_clk is a series of narrow pulses, one on each edge of the original clock. The pulses are evenly spaced only if the original clock had a 50% duty cycle.

So, the answer is no, you can't continue this indefinitely, since xor_clk is definitely not 50% duty cycle.

This is a very poor way to generate a clock, since the width of the pulses is determined by the logic delay of one LUT, plus some unknown routing delays. It won't be guaranteed that this clock will operate any other logic reliably -- you got lucky with your experiment.

The proper way to generate a high-speed clock is to use a PLL as a frequency multiplier. Most FPGAs include several PLLs for just this purpose. The fastest possible I/O speeds are in the tens of GHz on modern devices.

• Possible (FPGA specific) clarifications: (a) A PLL can allow a non-integer frequency multiplier, unlike the xor_clk which is just a doubler. (b) While the fastest possible I/O speeds are in the tens of GHz, I think that is the serial I/O from a hard IP SERDES. Whereas the user logic will use a parallel interface to the SERES at a lower clock rate. Dec 20, 2023 at 14:03
• @ChesterGillon: You can generate arbitrary I/O using a SERDES by feeding it the proper words generated by slower user logic. Dec 20, 2023 at 14:06