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I'm implementing a pipelined CPU in SystemVerilog. I need to propagate datapath signals from one pipeline stage to the next but, of course, not all stages produce the same number of signals.

To keep things tidied up, I group the signals in structs. Since each stage takes the signals from the previous one, adds a few of them, and propagates to the next stage, I have 2 options:

  • Create several different structs with a different number of signals, one per pipeline stage.
  • Create one big struct that contains all the possible signals, then set the unused ones to 0 in stages that don't use them.

I'm not sure which one to pick. The first one has the benefit of using less signals, potentially generating a smaller netlist after synthesis. The second one, however, is simpler/more regular and easier to understand and follow.

If this was a programming language, I would choose the simpler option and let the compiler optimize it. However, can I count on the HDL synthesizer to optimize out the signals that are always set to 0 and never read/used, in an more-or-less equivalent way as compilers do with source code?

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    \$\begingroup\$ My experiences are old. But bad. The HDL (VHDL and SystemVerilog) that I tried at the time (from XILINX for the 4000 series, so you know how long ago this was) were horrible at floorplanning. Not bad. But horrible. I mean... really bad. A stressed-out monkey could do better. (This was FPGA experience, obviously, and not ASIC.) And for gosh sake, read this. It's brings far more experience and modern experience to the picture. \$\endgroup\$ Commented Dec 21, 2023 at 11:19

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The synthesiser will remove all unconnected logic (unless explicitly forced to keep it). So if some signals are assigned in some stage, but unused downwards, the corresponding flipflops and combinatorial connections will be eliminated.

There is a slight problem, though. The synthesizer is likely to make a "notice" or "warning" about these removed signals. Synthesis logs are often flooded by such notices, and there is no automatic way to distinguish what is removed as intended, and what are design bugs.

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    \$\begingroup\$ In addition, constant values are propagated forward until they're actually used, eliminating logic where possible. For example, if you feed a 0 into an AND gate or the enable of a DFF, the gate is eliminated, the output becomes a constant, too, and the other input becomes an unused signal. The process repeats until all such reductions have been completed. \$\endgroup\$
    – Dave Tweed
    Commented Dec 21, 2023 at 13:55
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Combinational logic optimization in hardware and software is basically the same. It applies algebraic and Boolean expression evaluation to propagate constants and simplify logic equations.

Sequential logic optimization can be very specific to hardware design as well as the target technology the hardware is being mapped to. Even though the input to a DFF might be a constant, the output will not become a constant until the first clock edge. That may or may not be significant depending how power up reset is handled.

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