12
\$\begingroup\$

As a part of a controlled power supply for hardware-in-loop testing for a student driven project, I had to develop a current buffer (voltage follower) which could source up to 1 A.

I had the (bad) idea of trying to implement this simple circuit:

Initial circuit idea

The PMOS inside the feedback loop acts as an inverter (more V_gate, less V_out), and that's why the loop closes in the POSITIVE terminal of the opAmp instead of the negative.

In the lab I set VREF = 5V and VIN = 7V. I should get then 5V at VOUT, but I obtain this out-of-control output VOUT:

Vout

And this is the control signal (output of opAmp, connected to the gate of the MOSFET)

Vg

I find similar behaviors under different VREF, VIN and Rloads. Also note that the output of the opAmp is not saturated to any of the rails.

My assumption is that the gain of the loop is too high for keeping the opAmp in stability.

I have some background in control systems and opamps, but I don't know how to apply it to solve this situation...

Is it possible to apply some phase shift network to stabilize the loop?

I would appreciate both "quick hacks" or educational answers!

\$\endgroup\$
  • 1
    \$\begingroup\$ When I was in the breadboarding stage I achieved stability by using a parallel RC between the output of the opAmp and the gate of the mosfet: ![i.stack.imgur.com/5OJ0W.png] It solved the problem completely in the breadboard (blindly, I just saw a similar compensation circuit in an application note and it worked). But now that I have moved to PCB, the result is quite bad: ![i.stack.imgur.com/GnoSz.png] \$\endgroup\$ – svilches May 16 '13 at 19:40
  • 2
    \$\begingroup\$ See my answer, it explains where you went wrong - The good folk at all the great op-amp companies design op-amps that are reasonably stable with all manner of feedback regimes. Now, you've added a voltage gain stage of 100s and expect the op-amp to remain stable when you take the feedback point from the drain and expect it to perform without oscillation! \$\endgroup\$ – Andy aka May 16 '13 at 20:58
  • \$\begingroup\$ Thanks for all the insight! I have tried several of the stabilization method that you have proposed without too much improvement. It seems that the MOSFET adds just too much gain to the loop, making the stabilization quite difficult. I have tried the circuit from @Andy aka (source follower) and is completely stable in breadboard. I will test it tomorrow on PCB. The only drawback of the source follower configuration is that, for my application (6V, 0.5A output), I need a 12V rail (which increases the dissipation of the MOSFET) \$\endgroup\$ – svilches May 17 '13 at 12:16
11
\$\begingroup\$

This is really simple - use an N channel FET and have it as a source follower. You can even use a BJT. The one below has gain due to the 3k3 feedback and the 1k to ground from -Vin. If you don't want gain connect the output directly to -Vin and omit the 1k.

enter image description here

A unity gain buffer on the output of an op-amp is either an emitter follower or a source follower. Simple as that - feedback from the emitter/source back to inverting input of the op-amp.

Additionally, because the source/emitter voltage "follows" the op-amps output signal, the gate/base loading effects are minimal hence when using a MOSFET you don't need to worry about gate capacitance.

Think about this sensibly - Analog Devices or TI or MAXIM of LT - their marketing team are not going to wake up one morning and say to their designers - why can't you design an op-amp that allows someone to add a gain stage on it and expect it to be stable. If they did, the designers would say that they'd have to reduce the performance of the op-amp for it to be stable - just how would that op-amp compete in the market against all the op-amps that take the sensible road and keep building what they are good at.

\$\endgroup\$
  • \$\begingroup\$ Andy, the circuit you have posted is quite equivalent to mine... so I suppose that, if used with a MOSFET, it will have the same problems, am I wrong? \$\endgroup\$ – svilches May 16 '13 at 20:49
  • 2
    \$\begingroup\$ It is certainly NOT equivalent - OK my circuit uses a BJT but if instead it used a FET, it would be N channel type with the drain to +15V and the source to the load resistor. Feedback is also to the inverting input on mine. This circuit WORKS for the reasons in my answer. Sure, at 1st glance it looks similar but examine it again and listen to what I've said please. \$\endgroup\$ – Andy aka May 16 '13 at 20:53
  • \$\begingroup\$ @Andyaka The original circuit has a small advantage, and namely that to produce the voltage VREF on R14, the op-amp does not actually have to put out that voltage. It just has to turn on the PMOSFET sufficiently so that that voltage is produced on R14. But with your emitter/source follower, the op-amp has to basically produce the output voltage. \$\endgroup\$ – Kaz May 16 '13 at 20:56
  • \$\begingroup\$ @Andyaka But, of course, since the circuit is unity gain, the advantage isn't that great because the - input is driven to VREF. But suppose it is changed so there is gain. Then we can get an output voltage that is close to a rail, without driving either the input of the op-amp close to a rail, or its output. Just a thought. Using a PMOS or PNP for controlling the high-side of a load is not such a bad idea. \$\endgroup\$ – Kaz May 16 '13 at 20:59
  • \$\begingroup\$ @Andy aka Now I see your point, sorry! With the source follower there is no increased gain in the loop. Furthermore, Cgs doesn't matter because Vgs is small. I should have chosen this configuration at the beginning, fixing the PCB to change this is going to be quite horrible \$\endgroup\$ – svilches May 16 '13 at 21:11
11
\$\begingroup\$

Your op amp is oscillating because your open-loop gain is larger than 1 at a frequency at which the phase shift is 180°.

The op amp in your circuit is driving an almost entirely capacitive load - the MOSFET's gate.

There are many possible ways to correct this using just a well-placed resistor or a capacitor. It might be best to use a series resistor or a parallel RC shunt, or a feedback RC pair - it all depends on the particular circuit in question.

enter image description here

For more on this, refer to this excellent article by Analog Devices.

\$\endgroup\$
  • \$\begingroup\$ Indeed this is the right answer. And more in-depth discussion [here] on electronics.stackexchange.com/questions/146531/… \$\endgroup\$ – Fizz Nov 25 '15 at 12:11
  • \$\begingroup\$ Oh, cow, he is providing positive feedback to the opamp. Of course it will oscillate no matter what. Andy is right. This is actually a newbie mistake and everyone [else] was treating the [much more] difficult problem. \$\endgroup\$ – Fizz Nov 25 '15 at 12:46
  • \$\begingroup\$ Would you please update the "Analog Devices" link or give more description them we could google the article, please? \$\endgroup\$ – Mehrad Dec 7 '15 at 4:48
8
\$\begingroup\$

NOTE: This post has been extensively edited to add depth and clarity. While composing the original answer, a lot of details were considered that were not included to keep things brief. Here the skin is ripped off of the diagnostic and solution process to show what goes on under the surface and add substance. Think of it as a sort of diary of analysis. I'm leaving the original answer intact for transparent edits, adding detail in and after old text.

As has been pointed out, the output impedance of the LM358 is interacting with \$C_{\text{iss}}\$ of the FET to place a pole at about 20kHz. Since the loop still has lots of gain there it oscillates.


Editorial commentary about the diagnostic:

Where does this 20kHz pole come from?

It is not from \$C_{\text{gs}}\$, because that pole will not show up until in the MHz. This is a common source amplifier with resistive load (\$R_{\text{14}}\$ in the drain and resistance in the gate circuit (call it \$R_g\$). Location of the dominant pole for this sort of amplifier is approximately:

\$F_p\$ ~ \$\frac{1}{\text{2$\pi $} R_{14} C_{\text{gd}} g_{\text{fs}} R_g}\$ ~ \$\frac{1}{\text{2$\pi $} \text{(1000)} \text{(150pF)} \text{(5)}\text{(10)}}\$ ~ 21.2kHz (close enough)

So, the pole comes from \$C_{\text{gd}}\$ the Miller capacitance, which is so important here as it is multiplied by FET transconductance (\$g_{\text{fs}}\$) and load resistance (\$R_{\text{14}}\$). Do a quick sum of loop phase shift to see that, best case, you would expect 45 degrees of phase margin left at 20kHz (LM358 -90, IRF9530 -180 -45 = -315 degrees). Already, at 20kHz, phase margin is at best the minimum you would ever want to see in your loop, being 45 degrees and it's probably less than that. OK, so far this is a total SWAG. Its scientific since I used a scientific calculator to multiply and divide, and its a wild guess since I haven't yet looked at the datasheet for the IRF9530, and haven't refreshed my memory of the LM358 Zo. It does give a quick indicator of likely source of problem for the OPs circuit.

Looking for the most simple ideas to improve the situation:

First tried to provide a simple solution for the original circuit, resulting in the two bulleted statements below. These are both band-aid approaches that can't be taken far enough to make any meaningful difference. The lesson here (that I should already know) is never provide band-aid solutions, since they are not worthwhile. There are of course ways to fix the original approach, but they are more fundamental and complicated.

Then (finally) I suggested a source follower based circuit as a place to start as a solution. This idea is sound, including the integrator cap and FET \$V_{\text{th}}\$ caveat. I'll show why this is true in the next editorial comment after the source follower schematic.

A couple of notes about the circuit I suggested:

  • R1 in series with the gate is just a convenience. It is very common in circuits like this to need to isolate the gate for troubleshooting or testing. Popping up a resistor is a 5 second operation. Lifting the lead of a TO-220 is much less convenient, do it more that a couple of times and you may even lift a pad. If you are using a surface mount part, with out the resistor you will be having to remove the FET.

  • I show a 1kOhm resistor for R15. Really though, considering the output impedance of the LM358, I would not use anything less than 10kOhm ... and might even go as high as 50kOhm.


You could try:

  • Lowering the output impedance of the amplifier (a lot) by adding an emitter follower buffer at the amp output.
  • Isolate the \$C_{\text{iss}}\$ of the FET by putting some resistance in series with the FET source (between the FET and Vin. This would be kind of a band-aid approach.

Since the + input of the amp is being used as the negative feedback point, you have complicated things. Normally you would want to use the OpAmp as an integrator with a feedback capacitor from OpAmp output to - input. That way you could control the amplifier crossover point so that the phase loss caused by the FET capacitance could be unimportant or compensated for.

You might start with something like this:

enter image description here

Choose a value for C10 that causes amplifier gain to cross zero gain at 1kHz or less for stability. Using a FET you won't be able to get more than about 3V with any load at the output. In which case you would have to look at using a BJT or higher Vin.


Editorial commentary about the source follower solution:

Here is how I thought about a basic design solution.

What do we know about what svilches is trying to do with his circuit? Well, he wants to use 7V to provide up to 5V with up to a 1 amp load, and he wants to have the output voltage track a control voltage (that he calls a reference voltage). Basically, wants a linear adjustable power supply using a LM358 opamp for loop error compensation and there is only 2 volts of head room (that will be a problem for the LM358).

We don't know what kind of modulation will control the reference. Will it be a ramp, a sine, or maybe a pulse or step modulation? Step is the worst, although if you plan for it is not that big a deal, so figure the reference input moves in steps.

We don't know much about the load either. Is it steady current, or pulsed? Well, svilches is vague about it ... just needs up to 1 amp. But usually, ill defined loads are not steady, so I'm going to expect pulses here too. Also, since this is a power supply I am surprised to see no output capacitance (\$C_o\$) in the circuit ... but we'll cover that later.

Two basic ways to go:

Either compensate the common source circuit to be stable, or switch to a source follower circuit. The first option has a lot of merit, but is more complicated and I was looking for the fastest and least complicated solution. Second option, the source follower is a simpler design because it is constrained. By constrained I mean changing from a pass element that buffers current and has voltage gain to one that buffers current and has (except for special circumstance defined by parasitic elements) unity voltage gain. The advantage of the common source circuit is that it is a low drop solution, which you loose with a source follower amplifier. So, the simple place to start is the source follower.

Problems using a source follower power stage here:

  • Only 2V of head room means a really low \$V_{\text{th}}\$ FET. Also, with \$V_{\text{ds}}\$ of 2V and current less than 1A, \$g_{\text{fs}}\$ will be low and \$C_{\text{gd}}\$ will be high.
  • Using a LM358. The output of the LM358 has problems, output impedance is high and doesn't handle capacitive loading well (I'll cover this a lot more in a bit). Also, the output of the LM358 won't get any closer than 1.2V to the 7V rail, leaving only 0.8V for FET \$V_{\text{gs}}\$ (take a look at Fig 10. of the LM358 datasheet to see that this is true). As I pointed out originally, don't expect more than 3V at the source of a standard FET with this circuit. Don't get too excited about using a BJT either because at 5mA into the base the maximum output from the OpAmp will be 5.6V, so a \$\beta\$ of at least 200 will be needed and that's with \$V_{\text{ce}}\$ of 2V. That P channel power stage is looking better all the time, but we'll keep going with the source follower. Side note about the LM358: National Semiconductor liked this amplifier enough to put it into at least 3 product lines LM124 (a quad) LM158 (a dual) and LM611 (a single with reference). Datasheets for the LM124 and LM158 aren't too clear about performance near crossover, but the LM611 datasheet is great ... see especially figures 29, 30, 35, and 36. Oh, and while you are at the LM611 datasheet, have a look at those example circuits that have integrator caps around the OpAmp.

To save time and keep things moving lets pretend that \$V_{\text{th}}\$ is OK and use a compliment to the IRF9530, the IRF520 as a model pass element.

From the datasheet for the IRF520 we see for \$V_{\text{ds}}\$ of 2V current about 1A that \$g_{\text{fs}}\$ ~ 1 and \$C_{\text{gd}}\$ ~ 150pF. Now, one of the benefits of the source follower amplifier is that is gets rid of \$C_{\text{gs}}\$ loading that the OpAmp will see (at least until capacitive loading is added to the source ... then it's a different story). It's \$C_{\text{gd}}\$ you need to be aware of.

\$C_{\text{gd}}\$ still provides direct loading of 150pF (for the IRF520) to the OpAmp output, an OpAmp which is already having trouble with 50pF. Take a look at Fig 8 of the LM358 datasheet. There you will see small signal voltage follower pulsed response of the LM358 with 50pF load. It shows an overshoot of 1.3 times the step input, and that means that the phase margin of the amplifier is 45 degrees.

When gain falls at 20dB/decade phase is 90 degrees if the nearest simple pole is a decade away. A simple pole will cause 90 degrees of phase shift over 2 decades centered with 45 degrees of shift at the pole.

So, effectively, there is a pole at the crossover frequency if the amplifier has a 50pF load. This is probably a combination of the pole caused by amplifier output impedance and capacitance, and the higher frequency poles that exist in the amplifier response that add up to contribute the extra phase shift. It doesn't matter though how all the phase shift got there, what matters is that some of it is directly attributed to the pole caused by amplifier output impedance and capacitive loading. 45 degrees with 50pF of load. But, \$C_{\text{gd}}\$ is 150pF, which will push the effective pole frequency back by about 1.5 octaves (1.6 octaves really, but why quibble over 0.1 octaves). 1.5 octaves is worth about 20 degrees of phase shift, so now the amplifier has only 25 degrees of phase margin. If 45 degrees of phase margin results in overshoot of 1.3 how much overshoot would be expected with 25 degrees of phase margin?

Here is a plot of step overshoot versus open loop phase margin for a unity gain unity feedback amplifier.

enter image description here

Locate 25 degrees of phase margin in the plot and see that it matches an overshoot of about 2.3. For this source follower circuit using a IRF520, you would expect a step input of 100mV at the reference voltage to cause an overshoot of 230mV on top of its 100mV response. That overshoot would turn into ringing at about 500kHz for an extended period. A current pulse on the output would have a similar effect of big overshoot followed by ringing at about 500kHz. This would be unacceptably lousy performance for most people.

How could all that ringing be reduced? Increase the phase margin. The easiest way to increase the phase margin is to add an integrator cap around the amplifier inside the unity feedback loop. Phase margin greater than 60 degrees would eliminate ringing, and you can get this by reducing Opamp gain by about 6dB.

A Likely Scenario

Recall that this is basically a power supply. Here is a likely scenario, if the source follower is built without an integrator cap. There will be some disturbance or pulsing on the output, and the circuit will ring. The user won't like that and will add some capacitance to the source. Maybe just 0.1uF. As capacitance loading is added to the source of the FET, gfs (low anyway because of low \$V_{\text{ds}}\$) will lose the ability to cover up \$C_{\text{gs}}\$. Capacitive load at the Opamp output will start to increase from 150pF, moving towards 500pF. The ringing with added capacitance at the source will get worse. The user won't like that either, and will try even more capacitance to load the source. By the time capacitance at the source has reached 1uF, the circuit most likely will no longer ring ... it will oscillate.

Since I expect capacitance to be added to the output of the circuit, I would size the integrator cap to lower the loop gain by 20dB or so.

\$\endgroup\$
  • \$\begingroup\$ -1 for suggesting the problem is still to do with gate capacitance. Read my answer. The circuit you propose is the one I suggest but because it is a source follower the source follows the gate and hence gate capacitance is no longer an issue. Because a source follower is unity gain and adds very little phase shift it works so adding the integration cap and R1 is pointless. In addition it is oscillating at closer to 60kHz. \$\endgroup\$ – Andy aka May 16 '13 at 22:39
  • 1
    \$\begingroup\$ @Andyaka, I wasn't happy with my answer, having left out details that led to my suggested starting point circuit. So, I made edits to it, adding detail to make things clear. It was my fault that you could not follow what I was trying to convey. You seem to have 4 points or concerns that are: 1) My starting point circuit is the same as the one you suggest. 2) The additional parts in my circuit (namely the integrator cap) are pointless. 3) FET Ciss is of no concern since pass element is a source follower. 4) The OPs common source circuit oscillated at ~60kHz. \$\endgroup\$ – gsills Jun 11 '13 at 17:17
  • 2
    \$\begingroup\$ Continuing: A brief response, points 1) and 2) are contradictory, it is either the same circuit or it is a similar but different circuit since it has extra stuff (integrator cap) in it. I would say its a different circuit with extra stuff that is crucial for good performance. Of course, this hinges on point 3) being wrong, which it is (see edits). About point 4), OK, exactly ... a pole at 20kHz would be expected to effect stability at ~60kHz given the rate of phase loss. \$\endgroup\$ – gsills Jun 11 '13 at 17:18
  • \$\begingroup\$ @gsills I have made a similar circuit (source follower) which have very low PM, rings w/out stopping. I made a compensation like yours, suggested elsewhere. May I ask if it is correct saying that the crossover is reduced to 1/(2pi*C10*(R15+R14)) ? If I understand well and the xover is right, the idea is to have the BW lower than the oscillation frequency. Moreover, I will assume that xover is the BW. I then should analyze overshoots and rise times to see the actual achieved BW. \$\endgroup\$ – thexeno Feb 11 '16 at 22:02
3
\$\begingroup\$

Assuming that the problem is the capacitive load (gate of the MOSFET) some ideas are:

  1. In audio amplifiers, the classic approach for defending against capacitive loads is the inclusion of an output inductor, often in series with a resistor. Just an idea to keep in mind: don't forget inductors as a way of isolating from capacitances.

  2. Ever notice how the data sheets of linear voltage regulators always recommend a bypass capacitor on the output? This helps with a capacitive load. While it seems like a paradox, the reasoning is that the deliberately planted capacitor has a higher capacitance which swamps the small capacitance of the load, thereby creating a dominant pole at a lower frequency. Try a capacitor from the output of the op-amp to ground, of 0.1uF to 1uF.

  3. Since you're using the + input for negative feedback, there is a big opportunity in this circuit to add Miller compensation in the form of a more local negative feedback loop: a capacitor connected from the op-amp's output to the - input, instead of to ground.

  4. Your output stage is common-source, and so it has gain! The op-amp already has gobs of open-loop gain, and you're adding more into the loop. Consider an output stage that doesn't add any more gain: see Andy Aka's answer.

\$\endgroup\$
2
\$\begingroup\$

Note: the following paragraph is somewhat incorrect, in the sense that your idea could (and does) work with some tweaks and in a lot of products, PMOS LDOs in particular; see the subsequent material. I'm leaving this paragraph here though because LvW replied to it.

Well, capacitive load is a difficult problem to deal with even in a correctly set-up circuit, but in your circuit [as drawn] you are providing positive feedback to the opamp! This will oscillate like crazy even in simulation... with the same predicted 5Vpp. Yeah the oscillation shape is a bit different in simulation, but what do you expect... no parasitics and LM358 has a rather basic SPICE model.

enter image description here


@LvW: I need to think a bit more about what exactly happens but see updated graph with Vgate plotted as well. Clearly it never reaches 5V so the opamp is never seeing actual negative feedback as this design purportedly does. So the opamp works like a comparator basically. There's also some phase shift between these two signals, but I'm not convinced that's the cause of the oscillation, rather I think it's "by design". I've tried adding some big (1K, even 10K) resistor on the gate, and it still oscillates the same.

enter image description here


Basically what you're trying to do is design a PMOS LDO! But you're doing it fairly wrong. You need to compensate it with a bypass cap of the right-ish size and ESR! Also, a PMOS LDO would take the feedback through a voltage divider. Here's my amateurish LDO design:

enter image description here

As usual with PMOS LDOs, the output cap ESR is critical and needs to be in a certain band. Look what happens if I lower it, for instance; starts to oscillate:

enter image description here

If ESR is too high, you're again in trouble; well for this load it does have to get pretty high before it oscillates on the other side of the safe band:

enter image description here

Actually, the only critical element in there is that compensation cap. A 10uF one with 0.1ohm ESR appears to work for a fairly large load range from 1K down to 5 ohms (which would give you the 1A output you wanted):

enter image description here

You'd get some bandwidth limitation from this cap of course.

\$\endgroup\$
  • \$\begingroup\$ Positive feedback? I think, the FET acts as a common source stage with inverting characteristics, does it not? \$\endgroup\$ – LvW Nov 25 '15 at 13:26
  • \$\begingroup\$ @LvW: see updated graph and paragraph added. \$\endgroup\$ – Fizz Nov 25 '15 at 13:35
  • \$\begingroup\$ @LvW: I sorta figured it out. It was not a terrible idea, but was reinventing a certain PMOS LDO wheel and not doing it very well. \$\endgroup\$ – Fizz Nov 25 '15 at 14:46
1
\$\begingroup\$

Your opamp is not stable probably because you are driving a capacitive load (gate capacitance). Remove C10 and lower the value of R15 to tens of ohms. You can also try using a different opamp. The datasheet of LM358 says:

Capacitive loads which are applied directly to the output of the amplifier reduce the loop stability margin. Values of 50 pF can be accommodated using the worst-case non-inverting unity gain connection. Large closed loop gains or resistive isolation should be used if larger load capacitance must be driven by the amplifier.

Input capacitance of IRF9530 is 500pF so you definitely need to put a small resistor between opamp's output and MOSFET's gate.

\$\endgroup\$
  • \$\begingroup\$ Supposedly, as the resistor between the output of the opamp and the mosfet is increased, the system becomes more stable, am I right? I have tried with different values of R15 (up to 500K) without a good result... \$\endgroup\$ – svilches May 16 '13 at 20:12
  • \$\begingroup\$ Is there any other way to stabilize the circuit? Maybe I am placing the resistor in the wrong part of the loop... \$\endgroup\$ – svilches May 16 '13 at 20:18

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.