# Poor efficiency of an H-bridge

I am simulating an H-bridge/class-D amplifier based on four GaN transistors with integrated gate drivers (NV6113 from Navitas). I am driving the gates via PWM signals where the PWM frequency is about 330 kHz and the signal frequency is about 30 kHz.

Basically, the circuit works and I get a sinusoidal output voltage across the load (although the filtering can of course be improved).

However, I don't understand why the efficiency is so poor. An effective power of 3 W results across the load Rload. However, the circuit draws a power of about 13 W from the bridge voltage V_SUPPLY_FB. The power dissipation of the four transistors is around 2.5 W each.

I suspect the problem is that very high current peaks (10 A) occur in the drain current. Does anyone have any ideas on how the efficiency or the circuit could be improved?

Update 1:

I introduced about 18 ns of dead time. As before, an effective power of 3 W results across the load Rload. However, the circuit still draws an average power of about 8.1 W from the bridge voltage V_SUPPLY_FB (about 1.3 W average loss for each transistor). Thus, the efficiency improved from 23 % (without dead time) to 37 % (with dead time).

As the following signals (only shown for half-bridge) show there is still significant power loss in the transistors during switching. I noticed that the voltage on the first transistor only changes after the second transistor has been switched. Is this because the load has a relatively high impedance? Any ideas on how to further improve the efficiency?

Just for comparison the same signals without dead time:

• Do you have any cross conduction? Dec 21, 2023 at 21:27
• It is getting little shot-through every pwm pulse. You have to introduce a small dead-time between pwm pulses. Dec 21, 2023 at 22:31
• Datasheet: "Effective Output Capacitance, Energy Related" = 15pF ; FCV² = 0.8W so a large part of losses are from charging and discharging FET drain capacitance. This amp should be able to output 5A@400Vpeak so 1kW real watts, so 37% efficiency at 3W is pretty good. Dec 28, 2023 at 21:57
• @bobflux this would make a fine answer. Dec 28, 2023 at 22:07
• @TimWilliams Done! Dec 28, 2023 at 22:19

Datasheet says: "Effective Output Capacitance, Energy Related" = 15pF

Coss (Cds+Cgd) capacitance is charged from the power supply every time the FET turns off, which stores some energy. When the FET turns on, it shorts the cap so the energy turns into heat.

Power loss: FCV² = 0.8W with your numbers, so a large part of losses are from charging and discharging FET drain capacitance.

This amp should be able to output 5A@400Vpeak so 1kW real watts into a 80 ohm load. 37% efficiency at 3W is pretty good. It will be lower once you factor in the rest of low voltage circuits, opamps, gate drive, etc.

Also... I think the FET turns off and goes into diode mode where the arrow is pointing, so maybe you could reduce dead time. A bit more zoom wouldn't hurt to check. That will only matter for efficiency at high current though.

Along with Ohmic losses for cross conduction you have dynamic losses at each period T.

In fact, parasitic capacitors gets charged at VDD during T/2 and discharged to Ground from T/2 to T.

Evaluate both Ohmic and dynamic losses during a period T.