Problem understanding reset circuit for mini PCIe cards

Question

On my hands I have an Ekahau Sidekick 1, which is a device for measuring the Wi-Fi, and I've been analyzing its PCB for quite a moment now. It is composed of one main compute module(SMARC-FIMX6 from Embedian) and 3 mini PCIe card, two Wi-Fi adapters and one custom spectrum analyzer.

While looking at the PCB I spotted a strange area and drew the schematic for it(image attached to the post). The signal on the left comes from the compute module and the free signals on the right are going each to each mini PCIe module.

The question is: what is the purpose of all that mess? Why use a quad AND gate IC, if you will short all the inputs together anyway? And what's the purpose of this shmitt-trigger buffer with the diode and other components?

Answer 1

The NC7WZ17 and its associated components act to adjust the timing of the input signal. Low-to-high transitions are delayed by the R15-C7 network, and high-to-low transitions are passed with minimal delay due to D3 discharging C7 quickly.

U6 appears to be used just for fanout purposes. The AND gates are being used simply as buffers, to drive the three outputs. As I can't see the rest of the circuit, I can only speculate, but this may be so that other things that might drive one of the outputs don't affect the other outputs. The high resistance in series with each AND gate suggests that they want these to be weakly-driven signals; it's certainly much too high a resistance to function as line termination.

I'm not sure why they used a 74LVC08 quad AND gate in a large package when they could have used a 74LVC3G17 triple buffer in one of several tiny packages, but presumably they had some reason--maybe layout convenience, maybe the '08s are used elsewhere in the circuit, I couldn't say.

Answer 2

Why use a quad AND gate IC, if you will short all the inputs together anyway?

The question answers itself: you don't want the outputs to be shorted together. Nominally they should have the same logic state - that's what shorting the inputs does. Nominally :)

A big idea with PCI-E is that each slot is independent of the others. If the device in one slot fails such that it e.g. shorts the inputs to GND or something like that, you don't want the other devices to be affected. This may be only marginally relevant in a particular application, but hard-shorting multiple slots that can potentially experience hot-swap or temporary failures during development is not desirable. The independent drive is a nice conservative choice in a design where engineering time dominates the cost.

Sure you could use a single stronger gate and fan it out via 3k resistors. But it's not as if 4 gates really cost more. In the device you're speaking of, the engineering time is the main cost driver. The components such a gates are basically noise in the budget. It's an expensive, specialized product.

Answer 3

Let's start with the Schmitt-trigger buffer and what it's doing. Diode D3 and cap C7 are set up to delay the rising edge of RESETn locally to the board.

When SMARC_PCIE_A_RST goes:

• high-to-low, C7 discharges quickly through D3
• low-to-high, C7 charges slowly through R15

This effectively stretches the reset assertion time for the board.

Now, why did they use multiple AND buffers? Maybe for debugging and/or testability: they want to be able to reset a separate domain locally, so they split out the reset drivers so they can jam each one low (notice the 3k resistors on each gate for 'weak' drive.) There may be other reset drivers elsewhere that aren't being shown here.

Answer 4

As Hearth's alluded to, sometime it's just because you were already using AND gates elsewhere and didn't want to add a whole new line item to the Bill of Materials for a part you might only need one of.

I've certainly done this in some commercial applications (medical) where having a low BOM complexity was the bigger concern. When you're talking about product lines that span multiple decades, having a wider selection of parts just means you're more likely to run into obsolescence issues...

P.S. the quad AND gate may also just have been dirt-cheap and readily available from multiple suppliers (or already in their part library) when the board was being designed.

"It doesn't have to be perfect, it just has to work" - An engineer... probably