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While researching ESD protection on this site, I came across this question.

The answer by Peter Smith contains a comment by @Ale..chenski:

Just a nit pick: if you can afford 100R and 1nF to ground on a pin, you most likely don't need any extra ESD protection.

Can anyone elaborate on this? Is this really a valid protection or am I interpreting this comment wrong?

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    \$\begingroup\$ I guess it depends on your use case. How much you need protection and from what? And if your signal can or cannot pass an RC filter to begin with. There is no generic yes/no answer. \$\endgroup\$
    – Justme
    Dec 23, 2023 at 9:18
  • \$\begingroup\$ Not from a direct lightning strike to that IO pin. Depends on how much ESD you want to be able to protect it from. \$\endgroup\$ Dec 25, 2023 at 11:55
  • \$\begingroup\$ I don't think your propose filter will do very well against a lightning strike. We need to know how much charge and what voltage to give you an intelligent answer. \$\endgroup\$ Dec 28, 2023 at 19:51

4 Answers 4

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I don't quite like the answer either, and the comment seems out of context to me.

The values are certainly wrong: 100Ω, even if it doesn't arc over, has very little impact on a 330 to 1500 Ω ESD pulse, nor will 1nF take more than a modest chunk out of the 150 or 330 pF capacitance charged to many kV.

The values depend on the standard being tested; I use 150pF and 330Ω here, to represent the IEC 61000 Electromagnetic compatibility (EMC) Part 4-2: Testing and measurement techniques – Electrostatic discharge immunity test standard. (A complete model of the pulse waveform would require a more complex model, which isn't important to show here; the bulk of the pulse, and the charge balance, defined by R1 and C1, is most important here.) Different standards have different severity for a given voltage, so it is important to note the standard, or parameters used therein, when testing ESD.

That is, consider the impedance divider:

schematic

simulate this circuit – Schematic created using CircuitLab

We roughly model the ESD source as the left-hand components (SW1 + V1 set C1 initial condition, SW2 acts as trigger, switch or spark gap). 15kV is a worst-case figure, and 8 or even 4kV would be more typical, but in any case, notice the waveforms are essentially proportional, so scale accordingly to your application.

To be clear, the ESD node represents a connector pin or unshielded cable. It might also be a long unshielded trace on a PCB subject to induced ESD via coupling planes, or a cable subject to EFT (whether directly or by association).

To protect the pin, C2 needs to shunt this to maybe 10s of V. We measure:

enter image description here

The exact waveforms will vary, because ESD has a double-peak waveform (driven by transmission-line effects), and real environments likely have a lot of ringing too; but the general charge balance and slower-timescale current flows are what's really important here, and the steady value being some kV is damning. And, note that this puts over a kV peak across R2, which a chip resistor is not likely to survive -- probably arcing over, and it may blow up from this as well.

Bulk loading like this, is acceptable when the capacitance is some µF. This is why it's reasonably safe to clamp ESD into the supplies, for example: as long as the PDN (Power Distribution Network) impedance is nice and low at relevant frequencies (1s to 100s MHz), and has total capacitance of some µF, positive ESD can be shunted into the supply through a diode.

The issue I take with the answer is that, real diodes have ESR and ESL. Let's model the effect of that, too:

schematic

simulate this circuit

enter image description here

Without even modeling ESL, we see a peak voltage on D1 of about 20V. (Note the models in CircuitLab aren't especially accurate, but this isn't bad considering. Real diodes, the ESR partly depends on IF, while this model has a fixed about 0.5Ω ESR.) What's more, the PIN node has a source impedance of fractional ohms; we still haven't addressed ESD as such yet, and if we tie this to an IO pin, we're basically wiring the pin to supply with Thevenin equivalent of 20V 0.5Ω, and hoping that it isn't destroyed in the ~100ns this pulse lasts for.

The peak clamping voltage is a standard specification of real ESD diodes and TVSs, and typically lands in this range. Devices sometimes give dynamic or incremental resistance, of comparable value, as well (i.e., fractional ohm).

The best solution is to simply add another resistor between PIN and the IO pin as such. This limits current, so that the bulk of the pulse is shunted by D1/D2, and the source impedance seen by the pin is high enough that, whatever's left, isn't dangerous -- it will still activate the internal ESD clamp diodes, and may cause disruption, but should not cause latchup. Or it might cause latchup, but not outright failure (but mind extenuating circumstances, like browning or shorting out the supply; a hiccup-mode current-limiting supply may prove helpful here).

Datasheets usually stipulate nominal operation only for injected current below some margin; the margin can be as low as 0mA for analog pins, so expect ADC measurements for example to be in error during the pulse, but, it should recover by the next sample or so. Likewise, latchup typically requires 100mA+ injection to trigger; but obviously, it depends on the device, so again, check the datasheet.

schematic

simulate this circuit

If we so much as move R2 to the other side of the clamp diodes, we solve the issue:

enter image description here

It's a simple change, it could even be a typo in the other answer, but the resistor before or after the diode makes a huge difference!

I've increased the value as well to get it under 100mA peak. Note that I can remove C2 for ESD purposes, because the diode begins conducting almost instantly. It is still desirable for EMC purposes, as the low impedance at high frequencies helps shunt RFI, if this should be a problem; it also loads the signal, and the ideal value is determined by a compromise between signal bandwidth and immunity.

The downside to this strategy is, often we still want to have resistance facing the connector, to dampen cable resonances -- improving RFI, and ensuring filtering value of the capacitor regardless of source impedance (i.e., with a resistor to dampen resonances, stray inductance won't resonate the capacitor at an undesirable frequency). This can be a resistor or ferrite bead, but either way it's an added component, and now we're up to five components just to protect one pin.

It's easy to want to compromise on protection and filtering here, but it's hard to make a meaningful compromise while still offering effective protection.

For this reason, you may find combination clamp-filter components, like ST's USBUF01W6, attractive. Resistor, capacitor and ferrite bead arrays are also handy, so that multiple pins can be filtered at once, using fewer components overall. Likewise, TVS arrays like Bourns CDSOT23-SRV05-4 and etc., which also provide a supply clamp diode, so that they can be used alone (without bias, the TVS's capacitance does load the signals slightly), or to bolster the surge immunity of the supply (i.e., it's still protected even if total capacitance is low).

A closing note, scope:

This applies to single-ended signals, such as GP inputs for modest bandwidth (including, say: pushbuttons, LEDs, I2C, USART or SPI up to modest baud rate, etc.), outputs with no or light loading (modest-size series resistor) (e.g. driving CMOS input pins), or general purpose outputs (low resistance and/or ferrite bead). It does not cover high bandwidth signals, like bleeding edge SPI (10s Mbps), differential pairs, or high speed (USB, LVDS, PCIe, etc.), or anything behind an interface (RS-485, CAN, Ethernet, etc.; for which other standard solutions exist, or robustness is higher in general).

It also may not be required where properly shielded cables are in use. If ESD strikes the ground/shield instead of the signal pin, and if the shield is married intimately to circuit ground plane, then no voltage is imposed upon the signals when the ESD pulse reaches the board and connector. (Clamping and/or filtering may still be desirable for charged-cable events, though.) Any impedance between shield and circuit ground, means voltage drop for the ~10s A surge, and cable impedance means some of that surge is coupled to the device pins. Yes, this includes USB, which is often shown with shield lifted (and almost always erroneously so).

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  • \$\begingroup\$ If you discuss the ESL of the protection components, you also shouldn't ignore the ESL of the strike source. IMO, the relation of these two makes a discussion of ESL irrelevant. In practice, as you show, a well placed ESD diode plus series resistor after it will take care of ESD. \$\endgroup\$
    – tobalt
    Dec 23, 2023 at 20:47
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    \$\begingroup\$ How so? dI/dt of the strike source is so high, its ESL is irrelevant, and it can be modeled as a current source for most any in-circuit purposes. The ESL of clamping devices to ground, however, is critical. (Unless you meant something else by "strike source"; I'm taking it to mean "ESD discharge" as the characteristics of the generator discharge waveform, and calibration target, specified in IEC 61000-4-2 sections 6 and B.) \$\endgroup\$ Dec 23, 2023 at 22:28
  • \$\begingroup\$ Yes you're right. The profile is specified in the IEC. And that makes ESL indeed relevant. I hadn't fully thought about it previously. I intuitively placed ESD diodes as close to the strike point with low-ESL layout.. Still, ESL could raise the clamp voltage briefly by dozens of V. I suppose most chips are relatively tolerant if the pin current exceeds abs max ratings for ~1 ns due to the diode ESL. \$\endgroup\$
    – tobalt
    Dec 24, 2023 at 8:19
  • \$\begingroup\$ Re "a 330 to 1500 Ω ESD pulse": An effective generator resistance of 330 to 1500 Ω? Perhaps make that clearer? Pulses aren't normally characterised by a resistance. \$\endgroup\$ Dec 25, 2023 at 10:01
  • \$\begingroup\$ @PeterMortensen EMC pulses are often characterized by their source impedance, or the component values used to construct them. I will add the standard for reference. \$\endgroup\$ Dec 25, 2023 at 13:12
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Microcontrollers have ESD protection circuits built in, and are actually tested. From my experience in process development at TI, I can tell you that ESD protection is not trivial and a lot of time was spent making it actually work. The protection structures are not just R-C circuits or simple clamp diodes. To my memory (not an expert), they're more like diode-connected transistors.

Check your manufacturer's datasheet; you should see ratings for different ESD models -- human body model (HBM) and charged device model (CDM). The older machine model is no longer widely used but may be mentioned in older datasheets.

Adding an R-C circuit probably wouldn't hurt, as it might give the internal protection device more time to turn on. But ESD is a complicated subject, and if you want real protection you're probably better off using a purpose-built device like a TVS diode. Note that for common ports like USB and HDMI there are specialized ICs available that provide all-in-one protection against ESD and other faults.

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ESD tests are performed on the pins of I/O connectors and not on internal pins of the chips.

ESD tests belong to a larger family of EMC tests.


Scenario 1:

The GPIO pin is, for some reason, routed directly to a pin of a connector. In this case R and C are not enough. You need a TVS transient voltage suppressor.

I use PESD24 and I test them with a Fast Transient Tester that is able to generate bursts +/- 2000 Volt.

I don't have an ESD gun but ESD signals don't carry much energy so I'm not worried.


Scenario 2

The GPIO pin is not routed to a pin of a connector. No EMC tests are required.


R and C do protect pins, that's true. To my opinion, if you want to pass EMC tests you need to add a TVS chip.


Modern CPU's GPIO pins come with ESD protection built-in.

Some manufacturers like TI and NXP, in their CPU datasheets, add a reference to the ESD norm to which their CPU's pin are compliant to.

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  • \$\begingroup\$ (1) I think you're getting some terms mixed up. For a CPU, do you mean a microprocessor (MPU) or a microcontroller (MCU)? A CPU is just a section of those devices. You must mean an MCU as they have GPIO pins but MPUs (almost all) don't. (2) Which MCUs have ESD protection built in? Almost all MCUs have GPIO pins with clamp diodes but they can't be classed as ESD protection, they're really for transient protection. \$\endgroup\$
    – TonyM
    Dec 23, 2023 at 22:53
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    \$\begingroup\$ When I designed ICs for Signetics and Philips Semiconductors we performed ESD tests on the internal pins. But it was part of the R&D for the fabrication technology to prove the active structures (call them "big honking leaky transistors," not just clamping diodes) that we attached to the pins in silicon. You're point is well taken, though, once a chip goes into production. At that point ESD tests were always on the external pins. \$\endgroup\$
    – JBH
    Dec 24, 2023 at 6:58
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    \$\begingroup\$ @JBH I love the "When I designed ICs for ..." :-) That alone is worth a comment upvote :-). \$\endgroup\$
    – Russell McMahon
    Dec 25, 2023 at 10:27
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RC low-pass filters are used for ESD protection, but they are usually used on lines that aren't directly exposed to ESD events. They are used on lines that could pick up energy from a distant ESD event through radiation, which is way less energy than a direct ESD event. Usually it's about preventing falsified data on digital lines and not about preventing physical destruction.

On lines that might experience direct ESD events, such RC combinations are probably not sufficient.

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