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In their CMOS VLSI Design, Weste and Harris give the following discussion of power gating a block of logic:

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I am in particular interested in understanding the need for output isolation here. Is the concern that, without these isolation AND gates (which, when the block is put to sleep, output solid 0s because \$\overline{Sleep} = 0\$), the outputs might float around and so drive switching events in downstream logic from this gated block? I am hoping for an explanation of what might go wrong if those ANDs weren't there.

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2 Answers 2

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The clue is:

When the block goes to sleep, the header switch turns off allowing \$V_{DDV}\$ to float and gradually sink to 0.

The capacitance associated with \$V_{DDV}\$ must discharge. This allows the inputs to the gated block's output transistors to decrease slowly through the linear region of these transistors causing the ouputs to become unpredictable, capable of momentarily taking on any value even in the forbidden region defined by CMOS logic threshhold voltages. Eventually V_{DDV} will be low enough to bring the outputs to a known value (0V).

More correctly, allowing VDDV to become 0V removes all VGS bias from the power-gated block. This will force the outputs into a high-impedance state (floating) while sleeping.

This will in turn cause connected downstream logic to be unpredictable.

Placing the AND logic (powered by \$V_{DD}\$) in between will force the ouputs to zero when SLEEP is asserted, allowing \$V_{DDV}\$ to go to zero slowly and the power-gated block to remain with high impedance outputs.

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  • \$\begingroup\$ Got you. Is there any concern about these outputs floating once \$V_{DDV}\$ sinks to 0? I am thinking about leakage through the header transistors, but perhaps we make the threshold voltages on the leakage transistors high enough that the \$V_{DDV}\$ node is close enough to GND that all outputs are indeed 0? Accepted, but would love to know what you think about this. \$\endgroup\$
    – EE18
    Commented Dec 25, 2023 at 0:13
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Well, for example, if one of the signals is "I have data for you", the downstream logic may attempt to interact with the powered-down logic to retrieve it.

But the text should also mention the power implications. CMOS gates whose inputs are in the forbidden zone may draw static current or even oscillate. Even if this causes no logical problem, if defeats the power saving objective. But an AND with one of its inputs low doesn't do anything unusual, regardless of what its other input is doing.

Edit in response to comment.

If the gates of the N-channel transistors in the powered-down block float to 0, none of those transistors are on, so they don't pull the outputs of the block to 0. And since the block is powered off, there's no power to drive them to 1, either. So, where the outputs float depends entirely on leakage currents. Those are unpredictable: time and temperature dependent. A femtoamp point defect that randomly activates and deactivates could cause a great deal of activity on a floating node, while having no significance at all for a properly driven one.

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  • \$\begingroup\$ Ah, so you are saying these outputs might float to some forbidden zone value (as inputs to some subsequent block which we can't see in the image) and thereby draw quiescent current there? I guess I can't quite see why these outputs would float. Wouldn't they all get dragged down to 0 anyway as the block discharges? Or would leakage within the block through the header switch transistors potentially get these outputs to some steady state nonzero voltage? \$\endgroup\$
    – EE18
    Commented Dec 24, 2023 at 14:07

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