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In my synthesis report, I see that several signals internal to the microblaze have been routed onto the clock tree.

Clock Information:
------------------
-----------------------------------------+---------------------------------------------------------------------------+-------+
Clock Signal                             | Clock buffer(FF name)                                                     | Load  |
-----------------------------------------+---------------------------------------------------------------------------+-------+
...
system_1/RS232/Interrupt                 | NONE(system_1/microblaze_0_intc/microblaze_0_intc/INTC_CORE_I/intr_sync_0)| 1     |
system_1/debug_module/Ext_JTAG_UPDATE    | NONE(system_1/debug_module/debug_module/MDM_Core_I1/PORT_Selector_3)      | 31    |
system_1/debug_module/debug_module/drck_i| BUFG                                                                      | 64    |
-----------------------------------------+---------------------------------------------------------------------------+-------+

How do the xilinx tools determine which signals are clocks and which are not clocks?

Is the above to be a cause for concern?

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That a signal should be treated as a clock or not is determine by your synthesis tool. If you have anything that is triggered on a rising edge or falling edge of a signal it will consider this to be a clock and synthesize the logic as such. You can add specific constraints to prevent it from doing it but unless you have a good reason don't.

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You should look at what the tool shows how it placed things, but for the most part it's easy to imagine those signals needing to be clock signals. An edge triggered Interrupt should probably go to a edge triggered FF, drck_i looks like it's a clock signal and Ext_JTAG_UPDATE looks like a ascync command signal. But this is after just a cursory scan.

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If, during synthesis, a signal has to be connected to a CK input of a buffer, it is considered as a clock signal.

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