5
\$\begingroup\$

How do I define a tented via-in-pad in a parts library in Eagle PCB? (Example of result here:)

Once I define the large pad underneath the QFN, I seem to be able to turn the soldermask on and off. However, once I turn the soldermask off, it seems impossible to just define little circular areas of soldermask (soldermask layer in Eagle is just tStop).

\$\endgroup\$
  • 1
    \$\begingroup\$ Just out of curiosity, why would one want soldermask over a pad? \$\endgroup\$ – Andrey Nov 19 '10 at 13:15
  • 2
    \$\begingroup\$ @Andrey - Tented vias prevent traces from being shorted with a blob of solder or stray shaving of metal, reducing your risk of shorts to the actual IC pins instead of a random via on the other side of the board. He's not masking the pad itself, just the via. \$\endgroup\$ – Kevin Vermeer Nov 19 '10 at 15:16
  • \$\begingroup\$ In that case, this tutorial may help: sparkfun.com/tutorials/115 I'm not sure if you can do individual vias in Eagle like that, but you can play around with the limit value in the Masks tab of DRC, as well as the size of the vias. \$\endgroup\$ – Andrey Nov 19 '10 at 15:40
  • \$\begingroup\$ @Andrey, When you do not have tented via's underneath a chip the amount of solder you need to put the chip down can be variable, as it can flow out through vias. This type of action can be suggested by the chip manufacturer. the CC1100 for example had a warning to use about this. \$\endgroup\$ – Kortuk Nov 19 '10 at 16:11
5
+25
\$\begingroup\$

If you're willing to live with octagonal soldermasks on your vias, then try the following:

  1. Define the SMD ground pad, and disable the stop mask.
  2. Place pads where you want your vias. Make the pads have the same characteristics as the vias you want. We will delete these pads later.
  3. Show the soldermask layer (tStop)
  4. Draw a polygon on the tStop layer in strips. This is to prevent your polygons from enclosing any area, and so that it's easier to draw. If you want a 3x3 grid of vias, then you would need four polygons.
  5. Delete pads used as a template. The package is now done.
  6. Place package in layout
  7. Place vias
  8. Use the "NAME" function to change the via net to the same net as the pad - probably "GND"
  9. Route vias / add pour My package in progress. You can see the dummy guide pins (green) and the STOP mask fill polygon

After this, you will have the vias on the correct net, and your soldermask will come out as you wanted. The drawbacks that I see are:

  • The vias must be manually placed in the final board
  • Each via must be renamed to the target net (I couldn't get the GROUP function to work).
  • The soldermask is an octagon instead of a circle
  • There isn't an automatic way to draw the STOP mask for the package
  • Each via gives an overlap error in DRC (can be ignored).
  • No easy way for a STOP mask on the bottom side without drawing it manually

I was able to get this to work using Eagle 5.1 in about 15-20 minutes, so not too bad.

A simple layout showing the finished STOP mask

|improve this answer|||||
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.