13
\$\begingroup\$

In circuits like the one below, I don't understand how the capacitor can handle voltage spikes. I heard that decoupling capacitors deal with spikes by absorbing more of the voltage, but I don't understand how the capacitor can reduce the voltage received by the load as the voltage is same between parallel circuits.

\$\endgroup\$
3
  • 1
    \$\begingroup\$ In the schematic above, it won’t as whatever the DC supply will put out will prevail (including spikes). If you however introduce some source impedance and trace or line resistance, the capacitor starts to have an effect for high frequencies. Have you tried to simulate or calculate it? \$\endgroup\$
    – winny
    Dec 28, 2023 at 19:16
  • 1
    \$\begingroup\$ Real wires between the DC power source and the decoupling have a non-zero resistance, so you have an RC circuit, which is a filter. Real wires also have a non-zero inductance, so it's more like a RLC circuit, which is an even better filter. Unfortunately, the same kinds of parasitic resistance and inductance exist in series with the capacitor itself, so practical capacitors are much worse at filtering things than ideal capacitors, especially at RF... \$\endgroup\$ Dec 29, 2023 at 14:26
  • \$\begingroup\$ You can check what it does e.g. in this circuit. (Click the switch to see the difference with/without the cap.) \$\endgroup\$
    – JimmyB
    Dec 30, 2023 at 13:09

7 Answers 7

25
\$\begingroup\$

The capacitor is not there to absorb voltage spikes. The purpose of the capacitor is to prevent the short-term variations in the load current from becoming voltage spikes. $$\Delta V = \frac{\Delta Q}{C} = \frac{I\Delta t}{C}$$ where \$I\Delta t\$ represents a short-term-current change. The larger C is, the smaller \$\Delta V\$ becomes.

In other words, the low impedance of the capacitor at high frequencies compensates for the battery's relatively high impedance, "shorting out" high-frequency phenomena being produced by the load.

\$\endgroup\$
14
\$\begingroup\$

The capacitor and power source appear in parallel in the schematic, but the schematic doesn't show parasitic inductance and resistance in the wiring. In reality the circuit might look more like this:

schematic

simulate this circuit – Schematic created using CircuitLab

The load can change its internal resistance very sharply, demanding sudden changes in current. The wiring between A and B (and back to the voltage source along the bottom) has inductance \$L\$, which permits the potential at B to freely rise and fall, but prevents the current \$I\$ around that loop from changing sharply.

Therefore, without capacitance \$C\$, if the load suddenly demands more current, the potential at B will momentarily fall, until inductance in the path eventually "catches up" to that demand. Then, when the load suddenly requires less current, node B's potential sharply rises above the supply's voltage, only returning to normal once inductance in the path permits current to settle at the load's required amount.

Capacitance \$C\$ has the exact opposite behaviour to inductance \$L\$. It is able to respond to changes in current through it instantly, but will not permit fast changes in voltage across it. This means that as load current demand changes, the capacitor tends to hold B's potential fixed, while simultaneously acting as a temporary source/sink of current, to accommodate the load's requirements in the short term.

This also has the benefit of preventing power supply fluctuations due to the load's changing demands from affecting other systems connected to the same supply further down the line.

In the circuit below, I simulate a load with fast-changing current requirements. By switching SW1 at 1kHz, load resistance flips between 1kΩ and 500Ω at 0.5ms intervals, which causes it to draw either 5mA or 10mA from the voltage source BAT1.

Switch SW2 closes at 3ms, which introduces supply decoupling capacitor C1.

schematic

simulate this circuit

Here's a plot of load current through ammeter AM1:

enter image description here

Nothing seems wrong with this, until you look at the potential of node B:

enter image description here

Prior to 3ms, without capacitor C1 in place, there are clear spikes in supply voltage across the load. These occur because parasitic inductance L1 opposes those sudden current transients. These changes to supply potential could be devastating to anything sensitive (like 5V logic ICs) connected to that supply, or at best simply cause them to misbehave.

When C1 is introduced, after 3ms, it successfully takes over current-supply duties during those transients, and keeps the load's supply potential steady. If we look at current in C1, we can see how it sinks and sources load current while inductance L1 initially cannot:

enter image description here

That large spike at 3ms is C1's initial charging current, as SW2 closes; ignore that. The small current spikes following 3ms are C1 sinking and sourcing the current necessary to maintain a constant potential at B, for those short periods until current through L1 can "catch up".

\$\endgroup\$
5
  • \$\begingroup\$ Nice explanation. This is how I intuitively understand it also. What it's not so clear to me is why sometimes peaks introduced in the power rails are so hard or almost imposible to clean with capacitors, even with several ceramic low ESR ones. I suppose that at some point they are not 'fast' enough, but adding more in parallel should at least produce some effect. After a small improvement nothing changes no matter what you do. \$\endgroup\$
    – Gos
    Dec 29, 2023 at 9:06
  • 1
    \$\begingroup\$ @Gos wiring inductance and bypass caps form an LC tank, and if current transients contain any harmonics near the tank's resonant frequency (which is very likely for sharp transients) you'll see overshooting or ringing. Adding more capacitance simply lowers resonant frequency, and won't necessarily attenuate fluctuations more than before. The best way to improve behaviour will always be to reduce supply inductance to the point where bypass capacitance can be tiny, and resonance occurs at a ridiculously high frequency. I suppose you could employ some damping, with series resistance. \$\endgroup\$ Dec 29, 2023 at 10:32
  • \$\begingroup\$ Ok, I understand, it forms a kind of LC oscillator. And I suppose that protoboards add some inductance. The recommendations I found is to add some small resistor in series to the power pins of the noisy component. Or better, get rid of it when posible. \$\endgroup\$
    – Gos
    Dec 29, 2023 at 14:53
  • \$\begingroup\$ @Gos, Maybe instead of a "small resistor in series to the power pins of the noisy component" you should add an inductor? \$\endgroup\$ Dec 30, 2023 at 9:01
  • \$\begingroup\$ @Simon, reading your explanations about the influence of parasitic inductance, I get the impression that it is something harmful in this case. But then why are there LC filters? \$\endgroup\$ Dec 30, 2023 at 9:04
12
\$\begingroup\$

You have drawn an ideal circuit, not a real world circuit, so in ideal world these things don't matter. In real world, they do.

For example wires are not superconductors, and electricity does not move infinitely fast in no time.

Real world wires have resistance which defines how much current you can draw at what voltage drop, and inductance which defines how long it takes before you can have the current you need. And electricity in wires flows only at about two thirds of the speed of light.

In real world, the power supply might be a switch mode power supply, which has switching spikes and ripple voltage on the output. A capacitor resists the voltage change by either absorbing or releasing current.

For a load like a microcontroller, ìt is not a DC load as it runs at some clock frequency like 10 MHz, so it takes a spike of current each clock cycle so it takes in pulses of current at 10 MHz.

As wires and PCB traces have inductance, they cannot provide the current quickly for each spike so voltage will sag at the current spike. A bypass cap right next to MCU has low inductance path to MCU so it can provide the momentary current needed by discharging and it charges back between the spikes.

\$\endgroup\$
7
\$\begingroup\$

They don't absorb the voltage; They suppress voltage spikes and maintain the voltage by sourcing and sinking current. Decoupling capacitors locally stiffen the power rails for the chip.

\$\endgroup\$
4
\$\begingroup\$

You are right in theory. The perfect DC power has no internal resistor so in theory the capacitor cannot absorb anything.

But in practice the DC power is not perfect and conductors have also a resistance. So adding a capacity create a RC first order low pass filter. The spike has hight frequency harmonic so the filter help here.

\$\endgroup\$
3
\$\begingroup\$

Basic idea

A decoupling capacitor can be considered as a "backup battery" that helps the power source when the load current spikes momentarily. The idea is not only electrical but widely used in life. In this way, we ensure a problem-free supply of water, food, money and other necessary things. A typical example is a water tower.

How to explore it

Here I will share a bit of methodology on how to explore this arrangement.

"Stopping" time

In principle, we must observe this process over time because capacitors are time-dynamic elements. But we are interested in a few key moments in time, and what happens between them is of no particular interest to us. So if we can stop time in those moments, we can explore what is going on without being bothered. We can do it if we temporarily replace the capacitor with a voltage source of the same voltage.

I have combined both techniques and synchronized them.

Little text between many frames

The usual technique for explaining circuits is "lots of text with little schematics". However, CircuitLab is so convenient and intuitive that it allows us to bring many key moments to life... "to fit a lot of schematics into a little text"... and this is the case here.

Visualized resistors

I have showed the idea by the arrangement below where a real voltage source V with a relatively low (11 Ω) internal resistance Rin supplies a resistor load RL with higher (100 Ω) resistance. Rin can also include the line (wire) resistance. To visualize the currents without complicating the circuit diagrams, I have combined the respective resistor and ammeter into a "visualized resistor". For this purpose, I have set the desired resistance as an ammeter parameter. So Rin=11 means an ammeter with 11 Ω internal resistance; RL=100 means an ammeter with 100 Ω resistance.

Comparison

The best way to see if a remedy really works is to compare the two configurations - without and with remedy. In our case, we need to examine both configurations - without and with backup capacitor.

RC-FILTER

Step-by-step exploring

These explanations are synchronized with the Time-Domain Simulation (Schematic 3) below.

No "capacitor"

Normal load: The schematic below shows that when we connect a 100 Ω load RL to a 10 V real voltage source with 11 Ω internal resistance Rin, the 90 mA load current "creates" a 1 V voltage drop across Rin which is subtracted from V, and 9 V remain for the load (from another viewpoint, Rin and RL form a voltage divider that slightly decreases the input voltage). This would not be such a big problem if the current was constant but...

schematic

simulate this circuit – Schematic created using CircuitLab

Current spike: ... unfortunately, loads (eg an audio amplifier) often increase their consumption in short moments of time. Here I have simulated this by reducing RL by almost two times. As a result, the current through the load increases twice and the voltage across the load drops by 1 V.

schematic

simulate this circuit

With "capacitor"

0th ms: When we connect the capacitor and turn on the power supply, at the first moment the capacitor is uncharged and the voltage across it is zero. All the current is diverted through the capacitor.

schematic

simulate this circuit

8th ms: The voltage across the capacitor starts to rise and some of the current is diverted through the load.

schematic

simulate this circuit

50th ms: Finally, the voltage across the capacitor reaches the value without the capacitor (9 V) and all the current is diverted through the load. As you might guess, I have first measured the voltage without the voltage source and then applied it to the voltage source connected.

schematic

simulate this circuit

70th ms (current spike): When the load sharply reduces its resistance (as above, in Schematic 1.2), the load current almost doubles, but this is at the expense of the "capacitor" C. We assume that its capacitance is large enough and there is no resistance in series (ESR), so its voltage hardly changes.

schematic

simulate this circuit

Exploring in time

The next schematics are synchronized with the step-by-step exploring scenario above. I have simulated the load-current spike by connecting a programmable (CSV) current sink in parallel to RL. At the 70th ms, it draws about 112 mA current for 5 ms.

No capacitor

schematic

simulate this circuit

There is a significant voltage drop...

STEP 4.1a

... when the current increases at 70th ms.

STEP 4.1b

With capacitor

schematic

simulate this circuit

The voltage drop is insignificant...

STEP 4.2a

... when the current increases.

STEP 4.2b

LC-FILTER

As we know, apart from source and conductor resistance, there is also parasitic inductance in the circuit. Here we need to understand what its role is - whether it is something harmful and we try to reduce it, or just the opposite - it is useful, and we try to increase it. For this purpose, I suggest that we repeat some of the experiments above but with an added inductance.

To make our experiments time-independent, I suggest we apply a trick similar to the one above by replacing the inductor with a current source of the same current.

Step-by-step exploring

When we turn on the power supply, at the first moment the "inductor" is uncharged and the current through it is zero. All the voltage is applied across the inductor.

schematic

simulate this circuit

Then the current begins increasing and the voltage across the "inductor" decreasing.

schematic

simulate this circuit

Finally, the current is maximum, and the voltage drop across the inductor is only 1 V.

schematic

simulate this circuit

Actually, at this moment, the "inductor" (current source) is equivalent to the 11 Ω resistor like in the RC filter above.

schematic

simulate this circuit

When the load sharply reduces its resistance as above, the load current almost doubles, but this is at the expense of the "capacitor" C.

schematic

simulate this circuit

And now something new. If the input voltage increases (with 1 V), nothing changes because the inductor does not allow the current to increase.

schematic

simulate this circuit

And vice versa, if the input voltage decreases (with 1 V), nothing changes again because the inductor does not allow the current to decrease.

schematic

simulate this circuit

Exploring in time

To immitate input voltage spikes, I have connected an input voltage source with 10 V DC offset and 1 V sawtooth AC voltage.

No inductor

schematic

simulate this circuit

There is significant load voltage variation caused by the input voltage variation.

STEP 5.1

With inductor...

schematic

simulate this circuit

The load voltage variation is almost imperceptible.

STEP 5.2

... and capacitor

schematic

simulate this circuit

The load voltage variation is really imperceptible.

STEP 5.3

Summary

“Decoupling" capacitor and inductor separate the load and source with respect to rapid (AC) changes in current, voltage or resistance. They do it in two different ways - the capacitor does it in parallel, the inductor does it in series.

Possible scenarios to solve the problem

There is indeed something paradoxical in all this, but when understood everything becomes logical. Here are the possible scenarios of solving the problem:

No C and L: Initially (with neither capacitor nor inductor connected) there is not much of a problem.

C -> L: We want things to be perfect and decide to (AC) separate the load from the source by connecting a capacitor in parallel to the load. But we see that they influence each other through the series resistance between them (it is not high enough for the AC variations to separate them). So we decide to add inductance between the load and the source (connecting them by an inductor).

L -> C: With the same success, we can first decide to (AC) separate the load from the source by connecting an inductor between them. Now the problem is that the load remains without a constant supply voltage. Therefore, we fix it by connecting a capacitor in parallel.

The role of the parasitic inductance

In practice, the wire connecting the source to the load always has some, albeit small, parasitic inductance that decouples the load from the source during rapid changes in input voltage and load resistance. Its role is controversial - it can be both positive and negative. In this case, this is a positive effect, and we only strengthen it by adding an inductor.

\$\endgroup\$
1
\$\begingroup\$

I understand spikes to mean voltages higher than the required voltage, way higher usually, and transient in nature which is why they are called spikes. These may be caused locally, from an inductance being switched for example or externally from EMI.

To deal with these you need something that can absorb that excess energy. It needs to react only to excess voltage and do it quick enough.

There are many techniques to do this depending on the circuit and amount of energy, zener diodes, voltage dependent resistors for example.

With any problem like this it is always better to tackle the problem at source if at all possible because tackling it downstream is often much more complicated.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.