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I'm currently having problem in understanding the dynamics of capacitor when it is in connection with an ideal diode. In the circuit below we can see a sinusoidal source of 40V peak to peak and a frequency of 1000.

enter image description here

This picture below is the source voltage. enter image description here Now my actually query is that, when we are working with clamper the capacitor must have a potential difference across its terminals which is equal to the input voltage which is 20V for this case.

Since we are thinking about ideal diode(although PSPICE does not have any ideal diode source but it works as the exponential model) and ideal source(as PSPICE works with sources). When the source voltage is in positive cycle the diode is in forward bias and that branch happens to act as a short circuit. So the right terminal of the capacitor must have 0V potential as it is in short circuit with ground and the left terminal adjusts itself with the supplied source voltage. Once the input voltage reaches its peak the potential difference across the capacitor is 20V and normally the clamping capacitor should maintain that 20V potential difference throughout. But here is where I am facing problem grasping its dynamics. That is when the source voltage declines from its peak to 0 the right terminal of the capacitor must decline to 0 as well since the other branch is short circuited and current won't flow through the resistor. So when the input voltage reaches back to 0V the potential difference across the capacitor also declines to 0V. Then how are we able to clamp the circuit?

Well there might be some misconceptions regarding my assumptions. I am not quite sure if these are the misunderstanding regarding my question or not. That is we are assuming that the source is ideal which is an impractical assumption. So in reality the source has internal resistance so it adjusts itself in such a way that even though the diode is in forward bias the capacitor is able to maintain that potential difference. Again the PSPICE model works quite well because the diode isn't ideal so it adjusts itself with the supplied voltage.

I hope I am able to interprete my query.

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That is when the source voltage declines from its peak to 0 the right terminal of the capacitor must decline to 0 as well since the other branch is short circuited and current won't flow through the resistor.

That's the source of your confusion. You are correct that at peak input voltage the left side of C8 is at +20 V and the right side at 0 V. As the left side starts to fall the voltage across the capacitor tends to remain constant so the right side will fall from 0 V to a negative value. If R26 is a very high value the output voltage would reach -40 V. In practice the load resistor will be taking some charge from the capacitor and you won't get the full 40 V.

This is a very simple voltage-doubler circuit.

Add the output voltage to the trace and watch the first few cycles after power on. You can also watch what happens if you power on at positive-going zero-cross, negative-going or at 90° or 270°.


From the comments:

still have a slight confusion....if capacitance is high then when the left terminal is about to increase from 0 to 20V but due to it beinh capacitor it should obstruct the change of Vc so shouldn't right terminal rise from 0V? and this causes forward bias?

schematic

simulate this circuit – Schematic created using CircuitLab

Figure 1. Simulation circuit.

enter image description here

Figure 2. Blue: input. Orange: output.

  • Note that the output starts to follow the rising input at 0° but soon D1 is forward biased and so it gets clamped at 0.7 V.
  • At 90° the input has reached peak and now starts to decrease. It can be seen that the output voltage starts to go down with the input. The traces now stabilise with almost 40 V across C1. (The "almost" is because D1 is costing 0.7 V and there will be a small discharge of C1 through R1.)
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  • \$\begingroup\$ ohh I got it when the capacitor tries to maintain that peak voltage its right side goes to below 0V which results in reverse bias \$\endgroup\$
    – MSKB
    Dec 28, 2023 at 21:16
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    \$\begingroup\$ Correct. I've always found it useful to think that capacitors "tend to keep the voltage across them constant" and inductors "tend to keep the current through them constant". \$\endgroup\$
    – Transistor
    Dec 28, 2023 at 21:47
  • \$\begingroup\$ I still have a slight confusion....if capacitance is high then when the left terminal is about to increase from 0 to 20V but due to it beinh capacitor it should obstruct the change of Vc so shouldn't right terminal rise from 0V? and this causes forward bias \$\endgroup\$
    – MSKB
    Dec 29, 2023 at 11:58

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