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Many of the parallel memory chips I’ve come across have counterintuitive address line pinouts. Take the AT28C256 32KB EEPROM, for example:

AT28C256 DIP-28 Pinout

The data pins are in near-ascending order (only interrupted by GND), and address pins for A0-A7 are also grouped in an expected manner, but the rest of the address pins are scattered. This is a JEDEC standard pinout, so there must be a reason for it, but I can’t make any sense of it. Why not assign address lines A0-A14 to adjacent pins on the package?

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3 Answers 3

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That is for historical reasons how these evolved and the naming conventions were just extended as memory sizes grew and needed larger packages with more pins.

First you had smaller RAMs which had less pins. As an example, if you chop off the two top rows away and put VCC in place of A13, the alignment is even better, it almost matches the pinout of 24-pin SRAM. Chop off one row again and it will almost match 22-pin SRAM pinout, just the WE needs to be moved somewhere else.

And it's not just about SRAM chips as there are also ROM chips that share similar pinouts.

The reason why the data pins are at bottom end and address pins at the top end is that you can have neat distinction of 8 parallel data wires and some amount of parallel address wires flowing linearly between two chips.

So there is less crosstalk from address to data lines. Sure you could have data pins on left side and address pins on the right side, but making a PCB will cause alternating data and address wires then.

And for most chips, the ground will be at bottom left pin and supply at top right, so why change that.

In retrospect, I should have mentioned in the beginning, that if you talk only about RAM chips, the pinout does not matter. You can wire any address pin and any data pin however you wish, because they do not matter. Whatever bit pattern of data you want to write to any address represented by a bit pattern on address bus, it will be written and read back as-is.

For ROM chips it does matter, because if you want to burn or order a masked ROM with some data in some address, you need to connect it in the same way to match the data addresses and data bit patterns.

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    \$\begingroup\$ "if you talk only about RAM chips, the pinout does not matter. You can wire any address pin and any data pin however you wish" - Agreed for data, but for address there may be a performance penalty for switching address regions. Not sure about SRAM, but it's a concern for DRAM. And for EEPROM, you may have to deal with keeping data in erase blocks. \$\endgroup\$
    – marcelm
    Commented Dec 30, 2023 at 22:35
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    \$\begingroup\$ @marcelm Yes like I said it applies to RAM chips with similar pinout. DRAMs don't have similar pinouts so they do not apply. Except that early DRAMs could access only one byte per cycle anyway so same applied back then for DRAMs too. But I agree you have to anyway do the refresh properly. And early EEPROMs were byte writable too. The newer Flash technology were not and required block erases with commands through bus so they do require keeping address and data buses properly mapped for basic simple use. \$\endgroup\$
    – Justme
    Commented Dec 30, 2023 at 22:46
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Take a look at this diagram to see how the EPROM pin-out evolved: -

enter image description here

It evolved this way because that made sense (and still does). If you accept the ancient 2708's pin-out as being sensible then, adding more address lines follows a sensible evolving pattern.

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    \$\begingroup\$ I would think that having VDD be the twelfth pin up from the bottom in all package sizes would make more sense than having it always be the top right pin. Still, the desire to keep most pins in the same place for all package types drove a lot of the design. \$\endgroup\$
    – supercat
    Commented Dec 31, 2023 at 22:41
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Other answers cover the historical and upgrade-path aspects of this mapping.

But...

The exact assignment of the data and address lines to binary digits of the address doesn't matter for async SRAM at all. It matters for synchronous SRAM/DRAM only to the extent that there are out-of-band configuration data that needs to be exchanged between the host and the memory device, so the host needs to know what the mapping is, but it's otherwise arbitrary.

For PROM it only matters to the extent that both the programmer and the end user must agree on an order for data and address lines. It doesn't matter what it actually is. And certainly it doesn't need anything to do with the labels proffered in the datasheets for the parts.

In practice, given the constraints of 2-layer designs, you could tell designers that understood this from those who didn't. The ones who understood it would route with attention to layout, not address pin assignments. Compact layout had EMC, cost and reliability benefits.

Those who were less experienced would be beholden to arbitrary labels on the pin's chips, and the layout would take more space and have unnecessary complexity.

Sure, there's nothing wrong with "obeying" the labels in a datasheet - but they are arbitrary to begin with. As long as the actual mapping is documented for diagnostics and firmware PROM replacements and such, it's all good.

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    \$\begingroup\$ Thanks for including this particular point. It’s very relevant for me, as I’ve been struggling to make a clean routing using the assigned pins of a parallel SRAM chip. \$\endgroup\$
    – David D.
    Commented Dec 30, 2023 at 19:24
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    \$\begingroup\$ @DavidD. As far as SRAM and EPROM goes, consider all address lines to be mutually swappable, and all data lines as well. Sure you'll need to write a little script to re-shuffle the data for the EPROM to prepare a hex file to program it, but it's a minor inconvenience IMHO. \$\endgroup\$ Commented Dec 30, 2023 at 20:18

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