Synchronizing SPI ports for higher data rate

Question

I am designing a new board which uses the NXP LPC4330 (Cortex M4 microcontroller) with a XESS Xula2 FPGA development board. In this design, the Xula 2 has limited I/O pins since it is designed to fit into a DIP-40 form factor. The primary form of communication between the micro and the FPGA is through SPI.

I would like the bus to be fairly high speed, on the order of 80 to 100 Mbps. It might be enough to run a single SPI port at 80 MHz, but since the main clock on the FPGA is only running at 120 MHz (and it drives the SPI interface), I'm not sure that the SPI would work at such a high data rate. The LPC4330 has multiple SPI ports, and one idea I have is to use 2 SPI ports so that each can run at a slower bit rate. There is plenty of room on the Spartan 6 FPGA, but I do not have the I/O pins on the development board to have 2 sets of all 3 of MOSI/MISO/SCK (plus a single CS).

Therefore, I am wondering if it is possible to synchronize the ports on the LPC such that they share a SPI clock. The fast communication only has to happen in a single direction, so I would only need to double up the MISO pin (the micro needs to read quickly from the FPGA, not vice versa). There doesn't appear to be a special mode to synchronize the SPI ports, but I assume that they would be on the same clock domain due to the clocking architecture of the micro.

I realize there is also a multi-port SPIFI (spi-flash memory interface) on the NXP. Has anyone had an experience creating a block on the FPGA which basically emulates a SPI flash?

So my questions are a) do you think this will work? and b) is there a better way to do this?

Answer 1

Use SGPIO.

It contains 16 shift registers with 32 bits each and is very flexible in what it can do. You can chain up to 8 registers or run up to 8 inputs or outputs in parallel.

Answer 2

It may be possible to program one of your microcontroller's SPI ports as a master and one or more other ports as slaves. This would likely require physical wires interconnecting the clock pins for the SPI ports. SPI slave implementations sometimes have quirky timing restrictions and behaviors, but it should probably be possible for an SPI slave to handle any speed the SPI master could produce if both devices are running from the same source clock. If you use DMA, be certain that the SPI slave has higher priority than the SPI master. Otherwise if there's enough bus contention to delay a slave write but not a master write, the master could try to clock out data before the slave is ready with it.

Answer 3

I just read the specifications on the LPC4330 and it appears to support quad-SPI. This is a variant of SPI which uses clock, select and 4 bi-directional data lines to transfer 4 bytes per cycle.

This may be what you need.