1. While selecting a gate driver, how do we ensure that the sink and source currents are met so that the MOSFET will turn on properly?
  2. Also, how is the gate resistor related to this?

I have attached the datasheet of the MOSFET. If an example can be given with respect to it that would be great. The minimum Qg value is not provided so I was confused.

  • \$\begingroup\$ How fast do you need the MOSFET to switch? This, and the gate capacitance, determine the current you need. The gate resistor limits this current, and can prevent ringing (if any) caused by the PCB trace's inductance combined with the gate's capacitance. \$\endgroup\$
    – ocrdu
    Jan 5 at 7:49
  • \$\begingroup\$ To give a correct answer some application details need to be known. How fast does your application require the on or off speeds (i.e. rise and fall times) to be? Can different times be tolerable? Are there any paralleled MOSFETs? Are the gate traces long enough to cause some trouble? \$\endgroup\$ Jan 5 at 8:16
  • \$\begingroup\$ @RohatKılıç For double pulse test on the MOSFET. Tr and Tf in few nanoseconds (~ 30ns) \$\endgroup\$
    – Andr7
    Jan 5 at 8:29

4 Answers 4


We choose driver capacity and gate resistance to meet the required or tolerable minimum rise/fall time for the application.

What's tolerable, depends. If your application is hard-switched, and the layout is poor, switching may need to be quite slow to avoid excessive transient voltages/currents.

For example, suppose the given 120V 3.6mΩ D2PAK device is in a buck converter, switching against a schottky rectifier of comparable rating, in TO-247 package. Say the distance between components is 1cm, and the lead length of the TO-247 is another cm. Numerous ceramic capacitors are used nearby for bypass. Stray inductance is proportional to length, let's say 20nH. The schottky might have ballpark 1nF capacitance, and the transistor has ballpark 2nF Coss, so we have a switching loop with 1nF + 20nH at turn-on, and 2nF + 20nH at turn-off, or a characteristic impedance and time constant (λ/4) of 4.5 or 3.2Ω, and 7 or 10ns, respectively.

We draw an equivalent circuit something like this:

enter image description here
Source: own website, https://www.seventransistorlabs.com/Images/Snub5.png

In general, each element (Cin, Q, D) has some self-inductance, but without loss of generality, we can reduce it to a total loop inductance Ls (note ESLin is shown for illustration, but it too can be rolled into this). Thus we have two resonant circuits depending on which device is switched on at the moment: when Q is on, Vsw and Iin ring due to Ls and Cd; when D is on, Vs and Iin ring due to Ls and Cq.

The resulting resonant circuits have characteristic impedance \$Z_0 = \sqrt{\frac{L}{C}}\$ and (λ/4) time constant \$\tau = \frac{\pi \sqrt{L C}}{2}\$.

If load current is say 40A, then when the transistor turns off (if perfectly suddenly), we would have a peak of 40A * 3.2Ω = 128V. Conversely when the transistor turns on (if perfectly instant), the diode would see 180V peak. These are peak in addition to whatever the supply voltage is, mind, so both devices would most likely incur repetitive avalanche, and fail rapidly. There is also additional penalty due to nonlinear capacitance (at Q turn-on, D's capacitance is much higher, loading extra flux into Ls before it really gets swinging), or reverse recovery (applicable in minor part to some schottky diodes, and to all PN junction diodes).

We can reduce the peak voltage by turning on slower, allowing more time for the current to commutate between the transistor and diode loops, as governed by Ls. In 20ns for example, \$V = L \frac{dI}{dt}\$ or 20nH * 40A/20ns = 40V, and we could operate at 80V input, a very reasonable rating.

Or if we reduce loop length to more like 10nH (likely needing an SMT diode, preferably sync rect for much better efficiency), 15ns or so would be quite comfortable, and we could run maybe 90 or 100V input, even.

What gate drive strength is required to achieve this drain rise/fall time? Good question. Note that the transistor has gain. This is obviously true in the linear-amplifier case, but it's true in more abstract senses, like applying a band-limited square wave and getting a sharper one out. The output swings in only a fraction of the input; the rest of the gate voltage is used only to ensure full turn-on/off in the mean time.

In fact, the datasheet gives us Qsw, the gate switching charge. Note the diagram (fig.16 p.7), this is the charge required to go from just-beginning-to-conduct to more-or-less settled (with just a modest improvement in Rds(on) as gate voltage continues to rise). It's about a third of Qg(tot), so we can see it has about a gain of 3, and we can shoot for a risetime of more like 45ns, or an RC time constant of about 22ns, at the gate.

The gate equivalent capacitance is simply Qg(tot) / Vgs(on), or 16nF. To get 22ns time constant, we need a bit over 1Ω RG. This includes driver and internal resistance, and the latter is specified as 1.4Ω, so we probably won't get quite that fast in practice. (There's also the effect of common-source inductance limiting dI/dt, which I haven't covered here.)

Finally, switching loss will be in the ballpark given by the triangular approximation, \$P = V I t_r F_\text{sw}\$[1], or 80V * 40A * 15ns * Fsw = 48µJ * Fsw in this example. For Fsw = 100kHz, that's 4.8W, not bad (but enough that you'd want something easier heatsinked than a D2PAK, or, consider using several in parallel -- preferably as independent channels in a phase-interleave converter, which offers savings on input and output capacitors too). And this is for around 1.6kW input, so the efficiency of the transistor is quite good (the diode will be worse of course, having Vf ~ 1V).

[1] That's actually \$\frac{t_r + t_f}{2}\$, but I haven't specified different rise/fall at all so I'm hand-waving over that.

For ZVS/resonant converters, switching losses can be lower, and tolerable loop inductance somewhat higher, but they are more difficult to design and control.

So that's minimum Rg. As for maximum, rise/fall time simply goes up proportionally, and with it, switching loss.

This isn't very useful for SMPS application, outside of reducing EMI in certain nuisance cases -- and it's a poor solution at that, given the expense in power dissipation.

For general load-switching application, we might gladly slow the rise, perhaps to reduce peak inrush currents in load capacitance, perhaps to reduce peak overshoot voltage due to stray wiring, or to reduce emissions from long cables. It's not uncommon to use resistance more like kohms, even for a transistor of this size, to get edge rates in the 100s of µs, to suit such purposes. Note that, when the whole switching edge takes up the entire (transient) power dissipation rating of the device... now you have to mind SOA, and the problem becomes a hybrid switching and linear-amplifying case; choice of device may be determined by suitability for linear operation, or power dissipation or energy capability (die and package size), moreso than bulk ratings (Vds, Rds(on)).


You cannot determine the gate driver's minimum sink and source current requirement until you've specified how fast you want the MOSFET to switch.

If the switching time is very relaxed, the switching frequency low, and the drain current is low so it doesn't matter if the FET takes a long time to transition through the switching region, then the driver only needs to provide a suitable voltage. This must be well below Vth for off, and well above it, ideally above the voltage at which RDSon is specified, for on. The only current needed is to charge the gate capacitance, and mA, even uA, will do. I've seen slow designs where a single rail op-amp, or a 4000 series buffer, both of which will only manage a few mA, have been used.

If the FET must switch at 100s of kHz, then the energy dumped into its junction during switching must be minimised, and it's worth providing several amps of gate current to charge and discharge that gate capacitance as fast as possible. Most 'gate driver' ICs that I've seen will provide several amps of peak current to speed the FET through the dangerous Miller region.

There are two reasons you might want a few ohms to a few tens of ohms resistor in series with the gate.

Once you have a very low impedance driver connected to a high capacitance FET gate, ringing and damaging overshoots become possible, which could take your gate voltage above VGSmax. A few ohms will be needed to match the track between driver and FET, and control overshoots.

If the FET is fast enough, then very sharp current edges on the output may cause excessive EMI. Slowing the FET switching down slightly with a gate resistor is a cheap and effective way to reduce this EMI, as long as it doesn't switch so slowly that it heats excessively.


The MOSFET is a voltage controlled component. The gate-source voltage controls the drain-source resistance (and therefore the drain-source current).

The gate-source threshold voltage (typ. 3V) is the control voltage needed for a specific drain-source current (270uA).

Because the gate source of a MOSFET is highly capacitive, a gate resistor acts as a low pass filter for switching action of the MOSFET.



From your comment:

For double pulse test on the MOSFET. Tr and Tf in few nanoseconds (~ 30ns)

For such fast rise and fall times, the output resistance (or impedance, in general) of the driver also matters.

The input capacitance (Ciss) of your MOSFET, which is a gate-drive-voltage-dependent thing, and the output resistance of the driver form a RC network which also determine the switching speed.

Your MOSFET's input capacitance is ~10n which seems fairly high for a 120V MOSFET. If you use this driver, for example, you'll be right on the edge.

I don't know the details of the test so I'm not sure if there's a possibility of connecting multiple MOSFETs in parallel, but if that's the case then another gate stopper resistor will be needed and this will result in slower rise and fall.

So your main problem is not only the drive current but also the drive impedance and its effect on the switching speed.

  • \$\begingroup\$ Thankyou for your comment. Can you tell how do I calculate minimum Gate Resistor (output resistance) and the sink/source current requirements then? \$\endgroup\$
    – Andr7
    Jan 5 at 9:01
  • \$\begingroup\$ @Andr7 it's not a simple thing. The rise and fall times given in the MOSFET's datasheet for a gate stopper resistor of 1.6 Ohms can be a starting point (check Dynamic Characteristics section for details). This might tell us that a gate resistance of Rg = ~1 Ohm should meet your requirement. For a drive voltage of Vgs = 10 V, this makes the driver's peak output current ~10 Amps (i.e. Ipk = Vgs / Rg). So, you'll have to find a driver having a peak drive current capability of at least 10 Amps, or make your own totem pole / push pull driver. \$\endgroup\$ Jan 5 at 9:34

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