# OVP MOSFET Circuit

I've been trying to make a circuit that once a certain voltage (in this case around 7.1V) is supplied by the power supply, a MOSFET will disconnect the load from power. I know there are other alternative OVP circuits out there but I was curious to see if something like this would work. I haven't been able to simulate it in LTspice as the gate voltages I need for the circuit to work are rather finicky and none of the default models have the right values which is why I'm asking here.

The idea is during normal operating conditions, the divided pulls the gate of the n-channel mosfet low enough to keep it off, thus the gate of the p-channel MOSFET is pulled to ground, resulting in a V(gs) on the p-channel of -5 (meaning it will be on). Then once it is a high enough voltage the V(gs) of the n-channel is high enough to turn the MOSFET on. This shorts the gate of the p=channel to the source of the n-channel, which ver a range of 60V, should always be within 4V of the supply voltage. In the circuit the R2 resistor represents the load, R4 is to limit the current flow to keep the drain current of the n-channel low enough. By my calculations, this circuit should enter an OV condition at around 7.1V and should stop working (start conducting again) if the voltage reaches 60V.

If anyone knows if this would work or could point out any issues it would be greatly appreciated. (Edit; Fixed incorrect values)

• Looks okay at first glance but take a look at a typical datasheet for an NMOS transistor and note that the "on" threshold voltage is not all that predictable. They will often specify a maximum value at which the transistor is definitely on but there can be quite a range across individual transistors with the same part number. There will also be temperature variation. This makes it hard to target a specific voltage at which the circuit will be switched off.
– Tony
Jan 6 at 7:49

From a comment on the question, noting an issue with getting a deterministic NMOS transistor threshold voltage:

Looks okay at first glance but take a look at a typical datasheet for an NMOS transistor and note that the "on" threshold voltage is not all that predictable. They will often specify a maximum value at which the transistor is definitely on but there can be quite a range across individual transistors with the same part number. There will also be temperature variation. This makes it hard to target a specific voltage at which the circuit will be switched off. – Tony

I have seen a design which uses a Voltage regulator diode to set the overvoltage protection. E.g. from the schematic of the Advantech EVMK2HX Evaluation Module:

The analysis of the over-voltage protection circuit is that in the event of an over-voltage:

1. D8 conducts when the over-voltage causes the D8 breakdown voltage to be exceeded.
2. When D8 conducts Q9 turns on.
3. When Q9 turns on, Q20 is turned off.
4. When Q20 turns off, Q19 is turned off which disables power to the board.

The D8 BZX84-C12 part is specified with an approximately ±5 % (BZX84-C) tolerance range, so a min breakdown voltage of 11.4 V and a max of 12.6 V.

With a Q9 Vbe of 0.6 V (room temperature and an Ic of ~0.1 mA) that means the over-voltage protection could trigger from an input voltage of 11.4 V + 0.6 V to 12.6 + 0.6 V, i.e. 12.2 V to 13.2 V.

While this answer gives an analysis of a over-voltage protection for a 12 V supply, rather than the voltage of 7.1 V given in the question, it may serve as an example of a different circuit configuration to achieve an a more controlled threshold voltage using a Voltage regulator diode. The BZX84 series given as example:

• Is available in the normalized E24 ±1 % (BZX84-A), ±2 % (BZX84-B) and approximately ±5 % (BZX84-C) tolerance ranges.
• Includes 37 breakdown voltages with nominal working voltages from 2.4 V to 75 V