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I am currently developing an RF board that receives up to 8GHz. The board consists of a multi-layer structure combining Ro4003C (8mil) and FR-4. The connector I will be using for the RF board is a solderless connector, and I will be using the model 'NE06FS001' from waveguides. (See photo below)

NE06FS001

The board I am developing will mirror the GCPW structure presented by waveguides. waveguides presents the GCPW design shown in the photo below for the RO4003C (8 mil) using the NE06FS001.

RO4003C 8mil GCPW

The red boxed area in the photo above is where I'm having trouble. My board adds an FR-4 substrate underneath the RO4003C, should I do a through-hole via or just bilnd via to the RO4003C?

I'm also adding the datasheet of the connector for further advice. I expect the number of layers for RO4003C+FR-4 to be around 6.

+Added specific layer information. enter image description here

++What do you think of these processes? The idea is to add a single RO4003C board near the connector so that the connector GND is connected to the RF GND, and configure both sides of the RF path as blind via (layer1&layer2). enter image description here

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  • \$\begingroup\$ with-wave.com/end-launch-narrow-block <-- NE06FS001 datasheet \$\endgroup\$
    – hyerim
    Jan 10 at 8:14
  • \$\begingroup\$ Your question requires further clarification. Adding a side view of the required substrates and how you want them interconnected etc. would be useful... \$\endgroup\$
    – citizen
    Jan 10 at 9:42
  • \$\begingroup\$ Added specific layer information. \$\endgroup\$
    – hyerim
    Jan 11 at 0:30

2 Answers 2

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As the previous author suggested it is highly advisable to connect the connector GND to the substrate RF GND. In the configuration you have suggested the electromagnetic wave carried by the coplanar waveguide exists partly in the dielectric substrate (in the RO4003C), and partly in the air above it. So even though the CPW is on layer 1 with the energy carried mostly in between the signal track and the two side grounds, there is some also being carried through the air and immediately underneath deep in the Rogers dielectric. Your ground stitching proposed are neither correct nor incorrect. It really depends on how they appear to your HF signals. Generally, as you may or may not know, vias can be modeled as tiny inductors in series with your signal and in this case both length and via diameter will influence the total parasitic inductance. If you sprinkle more of the vias as advised by the manufacturer’s app notes you essentially place the many small parasitic inductances in parallel, thus reducing the overall parasitic inductance. The via length also tends to increase the parasitic inductance so you would be inclined to want to keep them as short as possible. Now summarizing the above leads to the following :

  1. Most of the HF signal’s EM energy is mostly found in the rogers dielectric between layers 1 and 2.
  2. Short vias add less lumped parasitic inductance, and more vias in parallel reduces overall total lumped parasitic inductance seen by your signal. So short and more vias seems to be generally better (not worse)…

Combining 1. and 2. above would suggest you’d achieve what you want with less parasitic inductance affecting your signal by the use of blind vias between layers 1 and 2 as this is where your signal’s energy is mainly propagating through from/to the connector. However if cost is your main concern you might consider the through vias as an alternative, keeping in mind that having your RF GND stitching going from layer 1 to layer 2 and then to layer 7 serves no benefit whatsoever for your RF signal, for the reasons already mentioned (or it might possibly degrade it to some extent). All your GNDs will eventually have to all meet-up at some point on your PCB but it may be not the best to do it right there at the RF connector end near the RF signal track of your GCPW etc.

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You should ensure wherever the connector GND contacts your PCB that it is also an RF GND. It looks like there's a piece underneath the connector that pulls it against the PCB.

So, yes, you'll want a through via.

You should also ensure that connector will fit on your stack-up.

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  • \$\begingroup\$ Thanks for the reply, I've added the specific layer information to my question, can you take a look at it? \$\endgroup\$
    – hyerim
    Jan 11 at 0:32
  • \$\begingroup\$ @hyerim I don't see thicknesses on your other stack-ups. \$\endgroup\$
    – Jason
    Jan 11 at 23:47

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