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I have a differential IF (intermediate frequency) signal generated by an ADL5801 RF mixer.

Stage 1: the signal is amplified before active filtering and it has LC LPF in the beginning for filtering unwanted frequencies above 2 MHz.

Stage 2: the signal is passed through a Sallen-Key HPF with -40 dB/dec, Fc= 400 KHz.

Stage 3: the signal needs more amplification because of filtering in stage 2. The gain is not fixed. It will be controlled by an MCU with a digital potentiometer. Stage 3 is suggested in this section as an answer to my other question which simplified the circuit.

ADC range is 0 - 3.3 V and max sampling frequency is 5.6 MHz or 3.3 MHz will be used. Signal frequency range of interest is 1 kHz to 1.5 MHz or so. 1.65 V is generated by an LDO which is stable with 10 μF output capacitance.

My questions are:

  1. Do I need biasing at stage 3 (ADA4807 part of the first schematic)? Is stage 3's design correct in general?

  2. Both the LT6232 and the ADA4807 have a low differential input resistance (7.5 kΩ and 35 kΩ). What resistor values should I select for gain, or do I need another op-amp?

ADA4807 Datasheet

LT6232 Datasheet

ADL5801 Datasheet

Schematic

Schematic 2

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  • \$\begingroup\$ I'm not sure why you have the first "differential gain" stage. You can combine the gain of that stage into the gain of the final stage. However, if you want two separate stages, the way you have it will also amplify the common mode signal. That is OK if there is no noise. However, if there is noise, amplifying it will only make it more difficult to remove later. If you want to amplify the differential signal only, use the circuit I provided in the previous question, but use a fixed resistor instead of a variable one. \$\endgroup\$
    – Math Keeps Me Busy
    Commented Jan 10 at 17:24
  • \$\begingroup\$ @MathKeepsMeBusy This IF signal is generated by radar application. It has high amplitude at low freq signals and further objects' signals are like microvolt and they are like noise on a low freq signals. Sallen key makes range compensation by decreasing low freq. amplitudes and increasing the higher ones. As a result high and low freq. have similar amplitudes. But after sallen key the overal peak to peak is low so another gain stage is needed. I undestand your comment. Could you verify if the especially last stage is correctly implemented. I did not bias any input just forwarded the signals \$\endgroup\$
    – Cenk
    Commented Jan 10 at 17:54
  • \$\begingroup\$ You do not need to bias the 3rd stage. The bias will "pass through" that stage and be present at the ADC. However, I agree with Andy aka that you may have problems using your digipot at high frequencies. High frequency automatic gain control (AGC) are often built around JFETs, and usually are applied early on in the signal chain, because the signal needs to be small to avoid non-linear effects from the JFET. \$\endgroup\$
    – Math Keeps Me Busy
    Commented Jan 10 at 18:21
  • \$\begingroup\$ @MathKeepsMeBusy Thank you so much. You helped me a lot. I might get rid of pot and use a fix gain at the last stage as well. \$\endgroup\$
    – Cenk
    Commented Jan 10 at 18:23

1 Answer 1

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Question 1

I don't think you need biasing but, if you plan to use the Digi-pot at anything above audio, the terminal capacitances of the wiper and A/B will become very significant. Have you looked at the capacitances in the data sheet? Why not try simulating stage 3 and see what I mean: -

enter image description here

I believe that the gain is likely to start to increase above audio (around 20 kHz) and become just too high at 1.5 MHz. Digi-pots are very difficult to use at these sorts of frequencies due to internal parasitic capacitances. Also, they have a natural imbalanced capacitance between A/B and wiper that might disturb the balanced signal you are trying to amplify.

Looking at your circuit a bit more reveals that you are using 10 kΩ feedback resistors in the stage 3 op-amps. The effect of this and 120 pF to ground on the wiper means a 3 dB increase in gain at 137 kHz. If this resistor was reduced to 1 kΩ that 3 dB change would occur at 1.37 MHz. You might be able to live with this but, if you can't then you'll just have to keep on lowering it.

But then you might run into op-amp loading problems and, the current into the Digi-pot input might exceed limits. Maybe you can also find a better low-capacitance Digi-pot. It's been a while since I looked so I can't recall what I chose but, my circuit was limited to 100 kHz.

Question 2

A low differential input resistance isn't as bad as what it seems; given that op-amps are used in linear applications, due to the virtual ground effect, both inputs of the op-amp will be at very close to the same voltage hence, the differential current into the op-amp inputs will be quite low.

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  • \$\begingroup\$ Thank you Andy i understood your points. 1-1.4 MHz is enough i will try to find a pt with lower capacitance to work with 10K or i will lower the resistor value. Can you verify the last stage, if it is correct. First two stages are working i know that. I added last gain stage after an answer i get here. In stage two there is 1.65v biasing from + input and since there is no cap series at the output of the opamp, the signal is dc+ac so no biasing is needed. This is what i tought so i implemented like this. \$\endgroup\$
    – Cenk
    Commented Jan 10 at 17:58
  • \$\begingroup\$ @Cenk please take note of this: What should I do when someone answers my question. I'll take a look afterwards. \$\endgroup\$
    – Andy aka
    Commented Jan 10 at 18:50
  • \$\begingroup\$ Back then i did not have ranking to vote and i always wait some more time in the case of another answer etc. before accepting. This is the reason i did not accept it and asked another question in the comment section. \$\endgroup\$
    – Cenk
    Commented Jan 10 at 19:04
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    \$\begingroup\$ Yes i searched it now and understand it. I will unpopulate R46, R49 (2.49K) and short R50, R51 (10K) to make it unity gain. It should be better in that way. I already have gain stage after sallen key filter stage. \$\endgroup\$
    – Cenk
    Commented Jan 10 at 21:36
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    \$\begingroup\$ You should double check the resonating effect of the LC I mentioned; it could damage the op-amp that follows if a transient signal was applied at the input. You need to have resistors in series with the inductors to lower the Q-factor is my main thought. Other than that it looks fine. \$\endgroup\$
    – Andy aka
    Commented Jan 11 at 10:06

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