The following is from the book Design of Analog CMOS Integrated Circuit, Page 307.
I think feedback is negative in my opinion.
Here is what I think, see picture below.
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\$\begingroup\$ negative feedback and your Vtest should be on gate of M2 and the signals go in CW direction. \$\endgroup\$– internetCommented Jan 13 at 21:58
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\$\begingroup\$ @internet Could you show your circuit analysis diagram? \$\endgroup\$– kileCommented Jan 13 at 22:39
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\$\begingroup\$ @internet "\$V_{test}\$ should be on gate of M2 and the signals go in CW direction." What do you mean CW direction? Isn't that the same as mine? \$\endgroup\$– kileCommented Jan 14 at 14:57
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2 Answers
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Simple analysis: Have a look at the closed loop (the loop gain with Vin=0) and find the number of signal inversions within the loop. For negative feedback, there must be an uneven number of inversions.
In your example: M1 does not cause a signal inversion between source and droain (common gate principle). However, and M2 in common source operation will cause a 180deg phase shift. T
Therefore, we have negative feedback (one single sign inversion).
Comment to your last figure: For loop gain analysis, you should try to find a node within the loop where a relatively low output resistance is connected to a much larger input resistance.
Then you can open the loop at this point and you can inject a test signal without changing too much the loading conditions at this point. Therefore, open the path at the gate of M2 and inject the test signal BETWEEN the drain node of M1 and the gate of M2. This is important, in particular, for loop gain simulation because otherwise you would destroy the DC operational point of the circuit.
However, for a rough loop gain analysis (visual inspection only) you can use the scheme as shown in the figure: Test voltage Vf at the gate of M2 and output at the drain of M1 (with Vin=0).
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\$\begingroup\$ What do you mean "output resistance is connected to a much larger input resistance"? Is \$R_{in} = R_{test}\$ and \$R_{out} = R_F\$? \$\endgroup\$– kileCommented Jan 14 at 12:33
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\$\begingroup\$ @kile A good breakpoint for injecting a test voltage is a point where the impedance, when looking in the forward direction, is much larger than the impedance when looking in the backward direction. You can find more details in Middlebrook's papers or lecture notes. \$\endgroup\$– internetCommented Jan 14 at 13:33
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\$\begingroup\$ @internet thank you for this additional explanation. That is eaxtly what I wanted to say. \$\endgroup\$– LvWCommented Jan 14 at 14:11
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\$\begingroup\$ @internet Can you draw your preferred test point diagram? \$\endgroup\$– kileCommented Jan 14 at 14:11
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\$\begingroup\$ @Lvw " open the path at the gate of M2 and inject the test signal BETWEEN the drain node of M1 and the gate of M2." Isn't that the same as my test point? \$\endgroup\$– kileCommented Jan 14 at 14:54
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It's negative feedback. M1 is sensitive to the difference between its gate and source voltages. Thus this device performs the 'subtraction' of the input and feedback signal (which is in phase with the input signal).
Another way of looking at this is from the viewpoint of M1's drain -- it inverts a signal coming in from the gate, while it does not invert a signal applied to the source (the feedback signal).
