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Changes in my design are forcing me to replace my 44-pin dsPIC33FFJ16MC304 with a 64-pin (same package size, finer pin pitch) dsPIC33FJ64MC506. In the datasheets for both chips, Microchip recommends a guard ring connected to ground around the oscillator circuit and a trace length of no more than 500 mils on the OSC lines.

The board is a 4-layer stackup (signal, ground, power, signal). I'm concerned about EMI because the board will be located near a compressor and two fans.

Pins 28-31 of the 44-pin package are +3.3V, DGND, OSC1, and OSC2. I currently have the oscillator circuit laid out like so: MC304 OSC

C10 is a 0.1 uF decoupling cap, C20 and C21 are the 18pF load caps for the 8MHz crystal Y1. I put the via to the ground plane at the end of the guard trace because Altium was treating it as an incomplete trace.

The decoupling capacitor placement is not optimal per Decoupling caps, PCB layout, but ignore that for a moment. On the new 64-pin chip, the pin arrangement changes to +3.3V, OSC1, OSC2, DGND.

It seems to me that the obvious location for the decoupling cap in this case is underneath the chip, but I'm restricted to placing components on the top layer only. That being said, I'm guessing I have to have C10 straddling C20 and C21 so that the power/ground lines go around the oscillator circuit. I don't like how long that will make the traces to the decoupling cap. For optimal EMC,

  • I intend to redraw the guard ring as a polygon pour to eliminate the extra terminating via. Where should I connect the guard ring to the ground plane, the single via in Olin's answer to Decoupling caps, PCB layout?
  • The guard ring connects to the ground pin on the PIC that the decoupling capacitor would normally be connected to. Do I connect the ground pin of the decoupling cap to the guard ring?
  • What if I avoid the longer decoupling cap trace length issue by using two caps (one for the power pin, one for the ground pin) like in How to connect decoupling capacitor when VCC/GND pins aren't close? Would this work better? My concern with this approach is how to connect the extra capacitor pins to the reference planes.
  • Do I increase the length of the OSC lines to better fan out the surrounding traces? It's currently about 320 mils from the MCU pins to the load capacitors, so I do have a little headroom there if needed.

EDIT: Here's the new chip pinout, no guard ring yet. Current OSC trace length is 416 mils. C29 in the picture is supposed to be decoupling the 3.3V and DGND pins on either side of the OSC pins. The decoupling cap is now a 0603 instead of a 0805 as well. enter image description here

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    \$\begingroup\$ Is it a display artifact or do you use thermal reliefs on your vias? The purpose of the thermal relief is only thermal, at the expense of an added, unwanted, inductance. If not required for soldering reasons, or other manufacturing reasons, I recommend to use solid vias instead. It will be better in EMC/EMI because of better decoupling. \$\endgroup\$ – Blup1980 May 21 '13 at 6:08
  • \$\begingroup\$ Good catch, that's from the default design rules in Altium. \$\endgroup\$ – Joe Baker May 21 '13 at 10:37
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What's the problem?

It isn't clear why you can't use your existing layout and just translate for the bigger package?

Guard rings are about DC...

The guard ring is designed to deal with leakage currents by placing a nearby intermediate voltage between sensitive sources.

The ground plane is for providing the low-inductance return path. If you are moving (returning) a substantial percentage of your signal on the guard ring, something is wrong.

Terminating your guard ring is not a hugely complicated concern, so don't over-think it.

Bypass what exactly?

The load capacitors/oscillator do not need an additional bypass. It doesn't do anything because there is nothing to bypass here.

The power loop for the oscillator includes the power entry pin to the PIC (bypass there), it's internal power distribution grid, the oscillator driver circuits, the oscillator tracks, and the crystal/osc itself.

Your bypass cap at the bottom of the second figure doesn't influence anything in that pathway. The answer you cite deals with a completely different scenario (the power pins of the IC itself, not I/O pins as in your scenario).

What to do:

  1. Single via at the extremity of the guard ring to ground plane
  2. Keep the crystal/osc lines as short as possible
  3. Place the load caps next to the crystal/osc -- turning them so that they are parallel to the long side of the crystal/osc with their ground pins facing each other is a good way to lower inductance, but it isn't critical to do so.
  4. Pour a small surface ground plane over the ground pads (don't forget thermal relief) and stich to the ground plane underneath with a few vias.
  5. Escape the nearby PIC pins via fanout and via to the lower surface for further travel (allows the lines to take up less y-space so that the crystal can be placed closer to the chip)
  6. Regarding C10 in the original figure. Just place it as close to (what looks like to me) pin #38 as possible. Don't worry about a cap near pin #41. It's covered by C10 even if C10 is a little further away.

Good luck! I'll follow-up if you have any further questions. Cheers.

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protected by markrages May 19 '13 at 7:45

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