I am trying to create a circuit for converting a variable frequency clock signal (with unknown duty cycle) to a pulse wave with an adjustable frequency-independent duty cycle. My approach is to create a sawtooth wave synced to the edge of the clock signal, and then generate the pulse wave by feeding a comparator with the saw wave and a threshold voltage equal to a fraction of the saw wave amplitude (e.g. 0.33V for a 1V saw for 33% duty cycle).

I have set up a saw oscillator which is reset using the positive edge of the input signal. However, if a simple constant charge current is used, the amplitude of the sawtooth will not be constant (lower for higher frequencies). I could then either try to adjust the charge current to ensure the amplitude is constant, or I could try to detect the amplitude and adjust the threshold voltage.

I the simulation below, I am using a simple peak detector to capture the sawtooth amplitude. This works great for a constant frequency, and also if the frequency is decreasing since the peak detector responds quickly to increasing amplitude. However, it will not adjust downward - unless I add the "low pass leak" resistor, which makes the capacitor discharge between the peaks. This is a poor solution though as it cannot both react quickly to changes in frequency, and at the same time remain constant during a period.

Simulation screenshot


Is there some smarter way to do the peak detector for this particular sawtooth case? The goal is to somehow latch the saw voltage just before it resets. I do have the edge detector pulse available, but it cannot be used directly since it is "too late"; once the transistor opens to sample the saw, the saw has already collapsed. Any ideas would be greatly appreciated!

Update: Some more details

This is for generating the gate signal in a synth sequencer. Therefore, the frequency range is incredibly low -- something like 0.1Hz to 10 Hz would probably be enough (6-600 BPM). The voltage range is 12V in general, but the input clock can sometimes be lower; let's say 5V minimum. The duty cycle range of say 1%-99% should probably cover any imaginable use case. Precision of duty cycle is probably not that crucial; I don't expect anyone to hear the difference of 1% length of notes. I imagine it is fairly important to keep the latency tight between the clock and the gate start (lets say 10 ms; 50 ms is probably acceptable too). Slope of edges is not that familiar to me, but going by the latency requirement above, 10 ms transition times would probably be acceptable, but the shorter the better.

  • \$\begingroup\$ change the order of edge detector pulse and 'ramp collapsor' \$\endgroup\$
    – Neil_UK
    Jan 16 at 14:28
  • \$\begingroup\$ Please clarify your specific problem or provide additional details to highlight exactly what you need. As it's currently written, it's hard to tell exactly what you're asking. \$\endgroup\$
    – Community Bot
    Jan 16 at 15:23
  • 2
    \$\begingroup\$ There are no specifications. What's the frequency range of operation? What's the precision and range of the adjustable duty cycle? What's the output voltage range? What's the input voltage range? What's the range of rise and fall times at the edges? Etc. Etc. \$\endgroup\$ Jan 16 at 15:57
  • \$\begingroup\$ @periblepsis Details added now. \$\endgroup\$
    – kalj
    Jan 16 at 20:18

1 Answer 1


Once I got my teeth into this, I couldn't let it go. I had a lot of fun thinking, and tinkering, and came up with an idea using a rudimentary sample and hold, instead of a peak detector. It relies on a square wave, with exactly 50% duty cycle, which I obtain from the not-50%-duty-cycle input like this:


simulate this circuit – Schematic created using CircuitLab

The flip-flop is anything that will toggle its output at each rising (or falling, but not both) clock edge. I've used a JK flip-flop here, but you could also use a D-latch, whose \$D\$ input is connected to its own \$\overline{Q}\$. The result is a Q output (node X) with exactly half the frequency of the input, and exactly 50% duty cycle.

Input \$V_{IN}\$ and potential \$V_X\$ at the flip-flop's Q output might look like this:

enter image description here enter image description here

Differentiators C1,R1 and C2,R2 produce short rising pulses and A and B, one in response to the rising edge of the flip-flop \$Q\$ output, and the other for \$\overline{Q}\$. Diodes prevent the pulses dropping too low, because they will drive BJT bases, and we should avoid severely reverse biasing their base-emitter junctions. This is \$V_A\$ and \$V_B\$:

enter image description here

\$V_A\$ is biased to have a quiescent value of -12V, which will be necessary for the sample-hold system, shown here:


simulate this circuit

The short positive going pulses at A from before are converted to much larger negative going pulses by Q1, which will be used to drive the MOSFET gates, at node Y. R4 and R5 scale \$V_Y\$, to swing between +12V and -4V, as shown here:

enter image description here

During the low periods of \$V_Y\$, the MOSFETs are switched on, connecting the source of voltage at C directly to capacitor C3, which will quickly charge to \$V_C\$. When \$V_Y\$ returns high, the MOSFETs switch off, and the capacitor holds that charge until the next sample is taken. With a sinusoidal input at C, this is how the module behaves:

enter image description here

Of course you could use an off-the-shelf sample-hold IC, or use an analogue switch, which would produce even better results. You should also buffer the signal at D with a voltage follower, since any load there will quickly discharge C3 between samples.

That's really everything new. If I use the sawtooth generator from your own design, putting everything together we have this:


simulate this circuit

The sawtooth generator is "reset" every other input cycle, and its output amplitude will vary with input frequency. We sample its output about half-way through its rise, so the sampled value should vary with frequency too, but now you don't have to wait for a peak-detector to decay. The response to frequency changes is pretty much instant, for rising and falling frequency. C and D change like this, as the input oscillates:

enter image description here

  • \$\begingroup\$ Awesome! However, in my case it is kind of a show stopper that the frequency is halved. Any ideas of how to work around that? \$\endgroup\$
    – kalj
    Jan 17 at 8:51
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    \$\begingroup\$ @kalj All I've done here is produce a voltage proportional to period, at D, to solve your problem, which was the slow decay of the peak detector. You don't have to use any of the other signals in my system here to produce the final output signal you're looking for. You can still use the original signal to produce a waveform of the same frequency, in whatever way you originally envisaged doing that, except now you also have D. My thinking was to use \$V_D\$ to set the charging current in another integrator, but that's where my brain stopped working. \$\endgroup\$ Jan 17 at 9:20
  • 1
    \$\begingroup\$ @kalj Also, it's possible to double the frequency first, then halve it. I'll ponder that for a while. \$\endgroup\$ Jan 17 at 9:23
  • \$\begingroup\$ I tried to combine this with my original oscillator: tinyurl.com/ywook99r (I should probably learn to use the CircuitLab thing). The nice thing is that sampling the half frequency oscillator mid-cycle gives a pretty good estimate of the peak value of the original oscillator, if the ramp slopes are matched. \$\endgroup\$
    – kalj
    Jan 17 at 16:26
  • \$\begingroup\$ @kalj CircuitLab is great for small circuits, but it's all JavaScript (and maybe some WebAssembly, I don't know), which makes it slow. It has limited functionality (for example DC opertaing points and sweeps are frequently bad, and component models are simplistic). It struggled on my PC to simulate that circuit. Having said that, it's amazingly useful for small modular tests, to check if you've made some stupid mistake, and its schematic quality is fantastic. It's by far the quickest way to test some idea, and show it to someone else. I love it most of the time, and occasionally I hate it. \$\endgroup\$ Jan 17 at 16:34

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