How to space stitching vias to avoid affecting the power plane?

Question

On a four-layer with the standard sig gnd pwr sig stackup, when flooding top and bottom layers with copper and stitching them to the ground plane, I know the standard rule is lambda/20 spacing for the vias. However, isn't there a risk of there being too many holes in the power plane and increasing its inductance/increasing the size of current loops? Is this typically negligible or is there a minimum spacing to follow?

Answer 1

power plane and increasing its inductance/increasing the size of current loops?

Yeah, cutting the plane does that, but the effect would be minimal. Let's say you cut back a 1sq" section back 50%. The DCR would be 0.41mΩ for no holes (0.5oz copper) and 0.82Ω of DCR with holes. Most digital or RF appications won't care about that.

For inductance for knocking 50% of the plane (lets say the plane has a 40mil spacing around the core) back you get 2.10 nH/in 1.15 nH/in, so unless you need the power plane to respond in the GHz range, it probably isn't going to make a difference with numbers.

On top of that the inductance and DCR numbers won't be that bad because most of the holes that would be put in the board would only give a 10-30% reduction in copper cross sectional area. Current loops won't really happen with a via fence, the current wouldn't have that far to go for it to be a problem as the holes would only be in the 10's of mil range and that wouldn't add a lot of inductance by having to go around the via vs straight through. Probably in the 10-100pH's, and that only matters for very high frequency signals if you were using the plane as a reference, but you wouldn't because you'd have to create a hole for the via fence if you were trying to run a signal through it.

Answer 2

Mind, there are no quick answers. The full solution lies in the space of EM field solutions, and it is your responsibility, as the engineer in charge of the design, to resolve those fields, making sure current return paths are short and wide enough, and so on. There cannot be a simple design rule that encompasses such level of detail. So, you are on the right track as far as suspecting an issue; there is not however a simple rule to solve it.

I suppose examples are as good as anything here -- to that end, here are some screenshots of designs I've worked on:

This is a 4-layer design, no outer pours or stitching, but shows how I've avoided grouping vias too closely together. Note that several routes would be tighter (purely in terms of physical length) if vias were allowed closer, however I prefer keeping them spaced so that no more than four in a row make a contiguous hole through both planes. (In fact the maximum run, over the whole board, is four vias; I should probably show those areas instead, or put another way, I'm cheating a bit by showing a region with a maximum run of three..!)

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Here's a, much more complicated design, accommodating a complex footprint, and multiple layers of both electrical and thermal connection. The best way to show it I think will be each layer at a time; bear with me:

Requirement was 1. use a ST powerSTEP01 stepper motor controller/driver chip; and 2. run it from a current-limiting / eFuse circuit for protection. This part has a somewhat complicated footprint, and in the interest of routing and compactness, it was routed on 4 layers. This makes complications for the supply (layer 3 / cyan), where the vias in the middle reduce cross section supplying the far corners. Conversely, vias in the corners (supply) and sides (outputs, bottom) reduce ground density, important as the ground-return path (via parallel shunt resistors, top) lies in the same place.

To improve things a bit, the vias are set in full pad-stack mode, with a 20 mil hole, 20 mil annulus on non-connecting layers, and 40 mil elsewhere.

This is actually a development version and I don't seem to have the final version files handy anymore; I think it ended up with more of smaller-diameter vias (which will also wick less solder than 20 mil i.d. vias do, important for correct solder dosing of these LGA pads).

Interestingly, this design was also a revision of a client original, which had been fabbed with via-in-pad (filled and capped vias), which looked very nice indeed and soldered easily but probably wasn't exactly the cheapest option(!).

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Here's another power design, a switching converter:

The design actually contains many plane layers (for unrelated reasons), most of which aren't interesting so I won't include them here, but the contrast between top and bottom allows me to illustrate a point.

What's pictured here is a DFN5060 MOSFET in a Ćuk converter; thermal vias tie top pour to two inner layers (which spread out heat, and current to connected components). Since so many layers are available, there is also ground poured around basically everything inside, allowing me to put thermal pour(s) inside as well, putting ground on the bottom layer as shielding (thus, the switching node isn't exposed to the outside as a patch antenna -- keeping EMI down).

The take-away here is simply: if a full perimeter of thermal vias were placed in the footprint, there would be a solid "slug" through the board stackup where no ground could fill under the MOSFET: both increasing its thermal resistance, and the inductance for the current return path underneath it (i.e. increasing inductance).

(The shaving-inner-layer-pads trick from above was not used here.)

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Regarding inductance:

Plane inductance isn't a huge concern in these examples, as the supply voltage, peak current, and switching speed are quite modest; for example, the powerSTEP at 80V, 10A and ~100ns, IIRC. Component placement is more than close enough.

A similar concern arises in the fanout of BGAs (I don't have any relevant screenshots to share here, unfortunately): nearly every ball gets a via, and each via necessarily drills a void straight through most or all plane layers. The plane coverage can go under 50% this way, and with peak currents in the 10s of A but with ripple required in the ~mV, even 10s of nH can be a huge deal.

If you can afford to use IOs near the periphery -- leaving most of the center unused -- you can keep plane impedance low; the only alternative is to use more planes in parallel. Putting figures to these is difficult; the inductance might be fractional nH, but at frequencies 100MHz and up, and impedances of ~mΩ, even that can be a lot.*

*Most BGAs are built on an interposer, which itself contains many plane layers, often includes bypass caps, or the die itself may integrate bypass caps on top; combined with the fact that pin/ball/pad inductances dominate (even for so many short-length elements in parallel), it's generally not required to have extremely low plane impedance above 100MHz. Put another way: whether or not it were our responsibility, as PCB designers, it's physically unrealistic to construct such low impedances (~mΩ) up to such frequencies -- if not outright impossible. Thus, they integrate in-package bypass by necessity.

Even if it's not impacting gross function (i.e. supply glitching), supply impedance still causes a secondary impact on signal quality: note that GND impedance results in common-mode emissions along signal lines. There's also any secondary effects, like timing jitter -- when it is critical, like custom high-speed interfaces with narrow eye diagrams, poor or no error correction, no facility for re-clocking / clock extraction, or the timing itself is critical (particle physics instruments for example).

Note that most commercially-used interfaces include such features (retiming, error correction, etc.; PCIe for example), making them much more robust to, well, commodity environments generally -- to be integrated into a wide spectrum of devices (consider the broad selection of PCIe-compatible peripherals available, or FPGAs and MCUs with PHY blocks integrated); to be laid out by shops not dedicated to high-speed and RF design; to be fabbed on lossy FR-4 PCB material; and to be mass-produced at consumer prices and quantities (servers, PCs, laptops, phones..). A ton of work went into making them very robust, and so they are tolerant of much meaner environments than you might think given some of the documentation on this topic [high-speed design].

Conversely, there are plenty of applications that do extent consideration deep into radio frequencies -- there are transceivers available with 433MHz, 900MHz, 2.45GHz, even more; where power and signal are routed directly from chip pins to board level, no (or minimal?) onboard bypass. The critical difference is, because they are low power (~mW say; even maybe some ~W peak for special cases, or for licensed operators), the impedances are far more manageable than for supplies of CPUs and such. Higher impedance means more slack in trace, pin and component body lengths, relative to the wavelength in question. Thus you might need dozens of parallel bypass caps mere ~mm away from an FPGA, but a low power 900MHz transmitter might be fine with a single cap 5mm away. (A power amplifier is also a heck of a lot simpler than a whole CPU core -- higher supply ripple may be tolerable, or just reduces to some impact on tuning impedance.)

Answer 3

This is not a direct answer to OP's question, but rather a counter example to what Tim Williams presented.

We had a high performance, multi-channel receive module that was experiencing coupling between some of the channels We were missing our isolation spec by ~25 dB.

The problem was traced to some missing stitching/ground vias between some of the layers. The picture below show the problem area. This is a RF coax connector to stripline feed.

The green dot is the via for the center conductor going down to the stripline layer. The white dots are the stitching vias; the pink is a ground trace on one layer, and the red is ground on another layer. The vias are placed 20 mil-30 mils apart (I forget the exact separation), and so we need two staggered rings of vias to meet the isolation requirement.

Looking at the top of the annular ring of vias, you can see that vias are missing. Adding the missing vias improved the isolation by ~35 dB.

We've had other instances were just a single or two missing vias caused us problems.

So the placement of stitching vias is highly dependent on your particular application.

Providing Some More Details on the Design

This was an RF module operating up to 20 GHz. It was implemented in an 18 layer LTCC hermetic package. And the isolation requirement between channels was greater than 35 dB. Note that we met the isolation requirement at lower frequencies, even with the missing vias, and only failed it at the top end.