I am designing a PCB using the AOZ2261NQI-12 buck regulator IC. I used UltraLibrarian to grab the ECAD files like I usually do, and everything looks kosher. However, when I place the part in a design it has two weird behaviors.

The first, and more concerning one, is that the pads seem to be registering as copper pours/traces instead of pads (I'm not sure the exact terminology to distinguish them - the point is they show up on the 'Top Copper' layer, but not on the 'Top Soldermask' layer). See below picture showing my .brd layout and corresponding Gerber generation. Any ideas as to why? My soldermask and solderpaste only include the tStop and tCReam layers, which the footprint doesn't include, but none of my libraries use those layers in their footprints so I assume Eagle does that for you automatically. I could make my own footprint for this chip and probably fix the issue, but I'm curious why it's happening in the first place.

enter image description here

The second issue, which might be stemming from the first issue, is that the middle pads of this chip are not pads in the library footprint file, but rather polygon pours. Therefore, I seem to be unable to connect all of the necessary pads to said pours. For example, the bottom pour is the LX node which connects to two LX pins on the bottom left of the IC and three more LX pins on the bottom right. With thermals off, my .brd polygon pours have no trouble encompassing the pins themselves, but they avoid the middle pours as if they were a different net. This can also be seen in the attached picture.

The problem here is that on page 4 of the datasheet it says to connect all the IN pins together, and page 14 of the datasheet illustrates that all LX pins should be similarly tied together in a large pour. So the ECAD files directly from the manufacturer seem to contradict the datasheet. Am I supposed to leave those separate pins unconnected on my board and assume they have sufficient internal connections? Or should I overwrite their ECAD files and make the footprint myself such that I can have them all encompassed by one pour?

Sorry this question ended up being so wordy. Hopefully I got my point across.

  • \$\begingroup\$ Create your own package. It is usually easier than troubleshooting and cleaning the UL generated ones. \$\endgroup\$
    – Lior Bilia
    Jan 19 at 20:30
  • \$\begingroup\$ @LiorBilia Thank you for your input. My second question still stands, but I'm moving forward assuming that they should be connected. \$\endgroup\$
    – InBedded16
    Jan 19 at 21:01
  • \$\begingroup\$ How thoroughly did you check the footprint to make things are kosher? Just glancing at the layers may not be enough. I seem to recall I ran into something similar with Ultralibrarian and OrCAD and I just fixed the footprint. \$\endgroup\$
    – DKNguyen
    Jan 19 at 22:49

1 Answer 1


That chip has a quite uncommon footprint. I'd recommend that you create the package yourself. There is a recommended land pattern sketch in the datasheet. Instead of using polygons, you could probably just use the normal pad object, one set for the exposed pads, another set for the edge pads. Then, in the device editor, you can connect the pins into the same net.

In EAGLE, the pad object normally automatically incudes the soldermask and solderpaste layers.If you use shapes or polygons,you need to manually create all of the layers. I suspect that UL has only created the copper layer.


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