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I am currently working on a STM32G071C8U7 microcontroller schematic and have some questions regarding the decoupling and general connectivity of the power supply pins.

  1. First I am presented with this diagram that clearly indicates how VDD/VDDA should be decoupled. However, I am not sure about VREF+/VREF decoupling capacitors. Is 1 uF recommended regardless of the intended use of VREF+ pin and 100 nF is only recommended if an external VREF is used? enter image description here
  2. If I understand this correctly, the analog power supply (VDDA) for ADC/DAC does not provide any reference and thus will not work if VREF+ is left floating with a 1 uF tied to ground. Based on that, if VREF+ is not connected to any other external voltage source it should be tied to VDD/VDDA, but decoupled with 1 uF (+ 100nF potentially). Is my thought process correct?
  3. Lastly, I am wondering what is the best known practice for this type of power supply configuration to improve power supply to analog peripherals or is it only gonna get as good as my VDD/VDDA decoupling capacitors and their placement relative to its pin/s.

NOTE: on this particular MCU part, VREF+ is not bonded with VDD/VDDA internally and has its own dedicated external pin.

Please find some additional documentation that I was able to extract from few documents: enter image description here enter image description here enter image description here

In this diagram it appears that VREF+ is not even connected to VDD/VDDA?

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  1. Data sheets and reference designs are just suggestions. Everywhere (AN5690, Discovery schematics) there are two caps shown on VREF+ pin, but sometimes there is 1uF and 100nF, sometimes 1uF and 10nF.

The actual bypassing also depends on if you plan to use the VREF+ pin as output or input, and if you are going to use it as input, then it is about if you connect it directly to VDD on PCB, or to some other supply for the reference voltage.

So if you don't know beforehand, just draw two caps on the PCB. Then validate your design how many caps you really need later. Or just leave in both caps as it likely does not matter if it is not required for operation.

The point is, you can apply as much or as little bypassing as you need for your design to work with good margin.

  1. Apparently not, because you can either connect it to VDD/VDDA yourself, or turn on an internal reference so the pin is an output and pin must be connected to caps only.

  2. Eval boards may be universal and the VREF+ may be connected to a jumper or solder bridge, which allows you to decide how to connect the reference pin, by moving jumper blocks around or soldering or unsolderint some blobs on the PCB. That can't be seen in the schematics as presented where the VREF+ is really going or is it left unconnected.

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