im having some trouble finding an example of the time-instability that motivates the flip-flop. wherever i look, the explanations are awfully airy-fairy (or at least my understanding is). for example, here they explain that there can be instability if the clock pulse is sampling from combinational circuits. im looking for a concrete example of such instability (i need these things explained to me like im a six-year-old kid), not just saying "things can be unstable". if i wrote in a maths exam "the given implication can be problematic" without providing a counter example i wouldnt get half a mark, and by the same token if i were authoring an article that discusses motivating flip-flops i would see it essential to "prove" their necessity.
my problem is that if i have worked out that if the [maximum] propogation delay for a given circuit, i dont need to wait for a clock pulse edge, i can just sample the output after that amount of time. meaning, even with a flip-flop i have to work out my clock-pulse speed, so why go to all the trouble of having 2 latches when i know that the desired ouput will exist after 1 pulse-length of time?
so if i had many different circuits that relied on each others output, instead of flip-flopping them all, i would just activate them in the relevant order according to a clock-pulse. im obviously missing something simple here because as far as i can see the flip-flop functioning to save from instability isnt necessary...
the JK flip-flop is a nice way to "regulate" the ouput because it solves an altogether different problem, that when j=k=1 the toggle that the JK latch would otherwise perform for the entire cycle that the clock-pulse is 1, happens only once, which means the final output is deterministic - as opposed to undefined. although that doesnt explain why its necessary on a D latch and an RS latch.
on that note, ill add a second question. whats the use of the JK latch/flip-flop? it seems to be introduced in many texts as an improvement on the RS latch, because of the problematic s=r=1 situation and resulting race condition. however if we setup the RS in a flip flop, we provide ourselves with a better alternative to the JK flip-flop: this acts like an RS latch but when r=s=1 on the clock's rising edge both Q and Q' are 0, and on the falling edge theres no change in the slave latch. so the problematic situation of r=s=1 becomes stable. the only advantage JK has over this setup is that r=s=1 actually provides a new functionality of toggle, im not sure if thats a desired thing or not...
hoping for some insight...