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im having some trouble finding an example of the time-instability that motivates the flip-flop. wherever i look, the explanations are awfully airy-fairy (or at least my understanding is). for example, here they explain that there can be instability if the clock pulse is sampling from combinational circuits. im looking for a concrete example of such instability (i need these things explained to me like im a six-year-old kid), not just saying "things can be unstable". if i wrote in a maths exam "the given implication can be problematic" without providing a counter example i wouldnt get half a mark, and by the same token if i were authoring an article that discusses motivating flip-flops i would see it essential to "prove" their necessity.

my problem is that if i have worked out that if the [maximum] propogation delay for a given circuit, i dont need to wait for a clock pulse edge, i can just sample the output after that amount of time. meaning, even with a flip-flop i have to work out my clock-pulse speed, so why go to all the trouble of having 2 latches when i know that the desired ouput will exist after 1 pulse-length of time?

so if i had many different circuits that relied on each others output, instead of flip-flopping them all, i would just activate them in the relevant order according to a clock-pulse. im obviously missing something simple here because as far as i can see the flip-flop functioning to save from instability isnt necessary...

the JK flip-flop is a nice way to "regulate" the ouput because it solves an altogether different problem, that when j=k=1 the toggle that the JK latch would otherwise perform for the entire cycle that the clock-pulse is 1, happens only once, which means the final output is deterministic - as opposed to undefined. although that doesnt explain why its necessary on a D latch and an RS latch.

on that note, ill add a second question. whats the use of the JK latch/flip-flop? it seems to be introduced in many texts as an improvement on the RS latch, because of the problematic s=r=1 situation and resulting race condition. however if we setup the RS in a flip flop, we provide ourselves with a better alternative to the JK flip-flop: this acts like an RS latch but when r=s=1 on the clock's rising edge both Q and Q' are 0, and on the falling edge theres no change in the slave latch. so the problematic situation of r=s=1 becomes stable. the only advantage JK has over this setup is that r=s=1 actually provides a new functionality of toggle, im not sure if thats a desired thing or not...

hoping for some insight...

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The master-slave arrangement doesn't strictly solve the metastability issue, AFAICT. It is commonly used to cross over between different clock domains of synchronous logic, but I don't quite see what improvement it does on purely asynchronous input (the slave gets a clear state, but it may be derived of a metastable transition anyway). It could simply be an incomplete description, as you could add a hysteresis function by combining the outputs of the two registers.

As for the differences between SR, JK, D or even T flip-flops, it tends to boil down to which inputs are asynchronous. The simplest SR latches do not toggle with S=R=1, but simply keep whichever state was kept last (or in the worst case, oscillate with a gate delay), that's the race. The JK, on the other hand, will transition on the clock edge - synchronous behaviour. It is thus their nature that a T register can only be synchronous, and an asynchronous D latch is transparent while latching. The SR register you describe doesn't have the T function, which can be useful depending on the function. For instance, a ripple counter can be described purely with T registers. Simply put, the JK gives you a complete set of operations (set, clear, toggle, and no-op) without costing an extra control line.

In synchronous logic, we frequently use wide sets of registers to implement a larger function. It doesn't strictly matter there if we use D, T, JK or whatever registers, as we can just redesign the logic function that drives them to include feedback (unless we need to build that logic - i.e. in 74 family logic). That's why FPGAs and such tend to have only D registers in their schematic representations. What does matter is that the register itself introduces the synchronous operation - steady state until the next clock. This allows combining plenty of side-by-side registers or ones with feedback functions.

As for the choice between delayed-pulse and clock-synchronous logic, it's not an automatic one. Some early computers (f.e. PDP-1) and even some highly energy efficient ones (f.e. GreenArrays) use the delayed-pulse design, and it is in fact comparable to a pipelined design in synchronous logic. The Carry-Save adder demonstrates the crucial difference - it's a pipelined design where you actually don't have a known value, not even intermediate, until the pulse from the last new value to enter has come out the other end. If you know at the logic design stage repeated accumulation but only the final sum is used, it may be the best choice. Meanwhile, FPGAs are typically designed with only a few clock nets and therefore do not adapt well to delayed-pulse logic (though it can be approximated with clock gating).

I hope this is more helpful than further confusing... interesting questions!

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  • \$\begingroup\$ thanks for your answer. some parts were a little above me, but it helped a lot. accepted. \$\endgroup\$ – davin Nov 20 '10 at 13:33
  • \$\begingroup\$ That might be a bit fast to accept it, especially if you still need clarification. Was there something particular that needs expanding on? \$\endgroup\$ – Yann Vernier Nov 20 '10 at 23:16
  • \$\begingroup\$ nope, your explanation that "the master-slave arrangement is user to cross-over different clock domains" and that regarding asynchronous logic there seemingly isnt an improvement essentially answered my question. add to that your last paragraph which explains that there is indeed place for delayed-pulse circuits over clock-synched ones, and we arrive at the conclusion that, as per my suspicion, the necessity for a master-slave latch is not inherent in all circuits. as per my second question, you confirmed that the T latch is a more complete package. \$\endgroup\$ – davin Nov 23 '10 at 10:36
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A latch may guarantee that if the clock input has a rising edge and remains high for at least Twidth, and the data input is high at least Tsetup before a rising clock edge and remains high for at least Thold after, then within Tpd the output of the latch will be high and remain so until the next rising clock edge. That does not mean, however, that the output of the latch will never change at a time more than Tpd removed from a rising clock edge.

In an ideal world, if a latching circuit receives a stimulus which may or may not cause it to change state, one of two things would always happen:

  1. The stimulus will visibly change the latch state immediately; the latch will remain in that particular changed state until the next stimulus.
  2. The stimulus will not change the latch state at all; the latch state will remain unchanged until the next stimulus.

Unfortunately, there's another possibility:

  1. The latch state may be changed in a way that is not by immediately or fully apparent for some time; the visible state may change at some arbitrary future time, unless a "clean" stimulus puts the latch into a known state.

To use a crude physical analogy, if a standing bowling pin is hit soundly, it will fall over immediately. If it's hit very weakly, it may be nudged slightly off vertical, but will quickly return to standing firmly. If it's hit somewhere in the middle, though, it may wobble around awhile before either returning to a steady upright state or toppling over. It may not be apparent for a over a second what the pin would end up doing if left undisturbed. The worst-case time to determine if a pin has been hit hard enough to topple it may far exceed the time that would be required to determine a clean hit or miss.

The closer a latch's stimulus is to one which would either almost or barely cause it to permanently change state, the longer it may take the latch to produce a cleanly-resolved output.

It would seem like it would be possible to design a latching circuit with a three-phase output, where the three phases were "high", "low", and "wobbly", and have downstream circuitry wait for the latch to produce a clean output before using the output value. Unfortunately--returning to the bowling analogy--while it may be possible to tell that a pin has fallen over sufficiently that it's not going to right itself, and it may be possible to tell that a pin has sufficiently stabilized that it's not going to fall unless it's hit again, there no clear and unambiguous way of establishing the moment where the pin's outcome becomes certain. No matter what one does, there will always be a theoretically-possible "trouble case". The best one can do, oftentimes, is let the pin sweeper come in and reset the state of the system, and hope there's no disagreement about whether the pin should be counted as having fallen before the pinsweeper got it.

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