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When there will be many (48) long (200 mm) overlapping PWM-signal traces driving separate LEDs, which merge together in a pad post-LEDs to then share a long (200 mm) trace back to a MOSFET switch leading to a non-grounded (battery-power) analog return, what should the stackup be (depiction at bottom of post)?

Less layers means less adjacencies to analog return. More layers means less adjacencies to signal return.

If LED.R, LED.G, and LED.B traces would directly overlap, should they instead be slightly offset such that the vertical path between signal and analog return or signal return is minimally impeded by other signal traces?

• 8 layers:

IC.top + V.bus
GND
LED.B
LED.RTN
LED.G
LED.R
GND
IC.bottom

• 10 layers:

IC.top + V.bus
GND
LED.B
GND      <-- added GND
LED.RTN
LED.G
GND      <-- added GND
LED.R
GND
IC.bottom

Detailed Information

I'm using an IC (TI TLC6983) to constant-current drive an LED array ([16xR + 16xG + 16xB] x [16scanline]).

Each scanline (01 to 16) is wired as follows:

3.0 V  20 mA   200 mm   LED       200 mm    MOSFET   artn
  o----( -> )----SS-----1>|---------SS-------[x]------l>
     |                  r01   |           scanline##
     |-( -> )----SS-----1>|---|
     |                  ...   |
     |-( -> )----SS-----1>|---|
                        r16   |
                              |
3.5 V                         |
  o----( -> )----SS-----1>|---|
     |                  g01   |
     |-( -> )----SS-----1>|---|
     |                  ...   |
     |-( -> )----SS-----1>|---|
                        g16   |
                              |
3.8 V                         |
  o----( -> )----SS-----1>|---|
     |                  b01   |
     |-( -> )----SS-----1>|---|
     |                  ...   |
     |-( -> )----SS-----1>|---|
                        b16

  o    : voltage source (bus)
( -> ) : current source
  SS   : length of wire
 1>|   : led
 [x]   : mosfet (switch)
 l>    : analog return

\$ f_{pwm}\ge 5\ \mathrm{kHz} \\ k_{pwmDuty.min}=\frac{1}{2^{15}}\cdot 100\%=0.00305\% \$

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  • \$\begingroup\$ Is this a PCB or FFC? Why do you need multiple layers? \$\endgroup\$
    – Voltage Spike
    Jan 24 at 19:25
  • \$\begingroup\$ @VoltageSpike : PCB. The LEDs are not arranged in a grid, so the 48 traces go to 8 locations on the board, each with a unique return trace. \$\endgroup\$
    – kando
    Jan 24 at 21:22
  • \$\begingroup\$ And what are the current specs of said LED's? \$\endgroup\$
    – Voltage Spike
    Jan 24 at 22:14
  • \$\begingroup\$ @VoltageSpike : OSRAM LRTBGVSR. Recommended current : 20 [mA]. I'm going to run them at that current and adjust PWM duty cycle for brightness. \$\endgroup\$
    – kando
    Jan 25 at 16:35
  • 1
    \$\begingroup\$ Any two conductors form capacitance, the question is how much? So adding two parallel traces in the stackup that cross over vertically over the length that are 10mmx1mm will have ~8pf of capacitance per cm. So what can the design tolerate, if you put a 100nf cap between any two LED signals would that be acceptable? \$\endgroup\$
    – Voltage Spike
    Jan 26 at 17:09

1 Answer 1

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At 5 kHz, even with a few higher-order harmonics, it's unlikely that you will reach much into 30 MHz and violate CISPR 22 limits.

enter image description here (Source)

8 and 10 layers seems excessive for any design. It is better to increase the copper weight than add multiple layers. Moving to a 10-layer design just to put in grounds for a 5 kHz signal adds unnecessary costs.

A 20mA signal with a requirement of a 10C rise time only needs a 12mil trace width with 1oz copper. 2oz would be 7 mil.

The real question will come down to the routing and minimizing cross capacitance a 1in square has capacitance in the 10-5 of range on most stack ups

Over 200mm this could add up. If you have the board space then do a 4 layer design and space traces horizontally. If you have to stack everything in a small area with a vertical stack up to minimize cross capacitance over long distances

IC.top + V.bus
GND
LED.B
LED.RTN
Power
LED.R
GND
Led.G
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