I have a product currently in the EMC testlab going through EN 55032 and EN 55035 (audio hardware) waiting to do the final tests on 61000-4-5 surge immunity. Up to this point, all tests have been passed on the worst test levels of industrial and residential level (B classes), along with high voltage bursts and ESD.

The device uses a custom linear power supply (not a pre-certified, off the shelf product). These final surge tests will be conducted in a week and I was wondering if there is something that I could or should do and bring a backup power supply with improved resilience, if necessary. There is still plenty of time for me to whip something up until then. Questions follow at the end.

/edit The following edits have been made to the post:

  • Updated spice schematic with all available parasitics of the transformer. I already had them included in the inductor parameters, except the leakage inductance, but extracted them now for improved clarity. See new simulations with leakage inductance at the very end.

  • I added a simple simulation of the slo-blo fuse and concluded it does not trigger through the surge (i.e. normal operation continues).

  • Added a CDN (coupling decoupling network) at the AC input, as defined in the IEC 61000-4-5 test setup.

  • I empirically plotted the ESR curve of the 1500uF capacitor. It has a value of ~250mΩ above 5kHz.

  • I removed the surge suppression component questions to focus on the main question.


This is the schematic of the power supply. It has no extra protection at this point, apart from a 100mA (@220V) slo-blo fuse on the L line at the input: Power supply schematic

(There is an EMI filter along the fuse inside the power entry connector receptacle.)

I measured the transformer and tried to run some simulations with the 61000-4-5 8/20 surge. This is kind of in between a trial-and-error and i-dont-know-what-Im-doing thing (note: I had to use LT3080 as there is no 2387 model for LTSpice). The circuit shown should be somewhat equivalent to the line-line test setup. Unfortunately, I cannot remember the exact Class that is being tested. I believe it is Class 3. Power is being tested on L-N, L-PE, N-PE at various voltage levels (0.5, 1.0, 2.0kV) and XLR ports are being tested on the shell only (2.0kV?). Therefore, as a worst case scenario, I'm using 2kV in the sim for all these tests: Spice setup

The diodes are SS1FN6, which have a IFsm of 40A@8ms.

The 1500uF capacitors are EEU-FS1V152. The manufacturer lists them as Low-ESR, with an impedance of 15m at 100kHz. They have 3.19A RMS ripple current. The measured ESR curve looks as follows and I picked 250mΩ for the simulation:

1500uF ESR curve

The transformer is the L01-6353 with 4kV isolation.

Now, according to the simulation, as far as I understand, the transformer "tanks" the voltage and generates a current spike on the secondary which is dissipated by the 1500uF capacitors.


The following simulation results were done before adding all the leakage inductances. These simulations only included inductance, DCR and parallel capacitance. See new results further down below.


The line-line test (see spice schematic above)

The surge on L line: Surge on L line

The current into the primary (118R series resistance, 5.5H): Primary current surge

The corresponding diode sees ~22A current on the secondary: Diode current

And finally, as the worst case, the 1500uF caps each see a ~10.5A surge: enter image description here

The line to PE test

Line to PE test setup

Surge on L line: Surge on L line

Diode peak is 14A and the caps have 7A peak each.

Running the tests on other points on the AC wave than the peak will drastically reduce the peak currents.


Running the simulation with the newly added leakage inductance shows that there is pretty much nothing left of the surge on the secondary side? I can't comment if this simulation is accurate at this point.

Current in the primary winding: Current in primary

Current in the secondary winding: Current in secondary

Current through 1500uF capacitor C1: Current through C1



A) Can the power supply, especially the capacitors, survive all the tests? Or am I being too naive to expect them to withstand?

B) Or should I install surge protection devices on the primary side?

You are welcome to highlight things I might have missed/misinterpreted or if I should go a different route etc.

Thank you very much!

  • 1
    \$\begingroup\$ If you have a week to testing, then the die is largely cast. Trips to the EMC labs are usually good learning experiences, and at this point I think you'll have to watch and see what happens. If you have two copies of your product, I'd bring both, along with a box full of MOVs, TVSs, GDTs and a soldering iron. When things fail at the lab, come prepared to experiment and come away with a good understanding of the problem and solution, so that your second trip is uneventful. \$\endgroup\$
    – Smith
    Jan 28 at 2:08
  • \$\begingroup\$ It looks relatively rugged, but carefully simulate (i.e. use realistic capacitor ESR, transformer coupling and LISN) the secondary voltage spike for the L-L surge. If that exceeds the abs. max. voltage of your regulators or capacitors, you might need to put a pair of TVS or MOVs there. \$\endgroup\$
    – tobalt
    Jan 28 at 7:35
  • \$\begingroup\$ regarding capacitor ESR: 100 khz is usually much lower than 120hz rating, but for the uptake of the surge charge, the 100 kHz value should be realistic. For good measure, maybe increase it by a factor of 3 or so to feel safe. \$\endgroup\$
    – tobalt
    Jan 28 at 7:41
  • \$\begingroup\$ regarding close votes: If it gets closed then because of lack of focus. In this case, I suggest you delete all the talk about TVS vs MOV from this question and focus on: Do I need protection and if so, where? MOV/TVS is discussed plenty on Internet and SE. Or you could make a new question yourself following the conclusion of this one. \$\endgroup\$
    – tobalt
    Jan 28 at 7:45
  • 1
    \$\begingroup\$ To check ESR v frequency in this way, it's better you use a sine wave as this will probe only a single frequency. With a square wave, you could be already limited somewhat by ESL near the edge. And I agree, 0.25 ohm for a 1500 µF Al electrolytic (even a regular one) at 10 kHz would be terrible. I would expect an order of magnitude lower. \$\endgroup\$
    – tobalt
    Jan 29 at 15:06

2 Answers 2


I will stay out of the noise filters, as they have ambiguous results unless elaborate and space consuming.

As far as TVS vs MOV, TVS handles tiny 5 kA surges that exist for only microseconds at most. The body is too small to dissipate accumulated heat, so use on phone and data lines is common. Low capacitance SMD versions are used on GHz speed coax and ethernet lines. These are not fused.

MOVS (20-40 mm) are perfect for surge suppression on AC power feeds, including use on circuit boards. TPMOVS have thermal protection built-in but are very expensive and bulky.

As for part numbers, there are two common ones in use.

Example 1) V150LA20AF Used by LITTLEFUSE and others. The V150 is the maximum allowed AC + DC peak voltage. This is safe with 125 VAC with a 15% overvoltage. The LA20 means has a 20 mm round body, which handles repeated 5 ka surges. Use 15 A fast-blow fuses in series in case of severe overloads.

Example 2) S20K250 Almost the same, with size and voltage swapped. Used by GE, Siemens and others. 40 mm MOVS are bulky and expensive, so are not normally used on circuit boards, but can handle repeated 20 ka surges.

Voltage chart, for most common AC outlets:

125 150 or 170
220-250 270 or 320
277 320
347 420
480-600 720

15 A fast-blow fuses MUST be used per UL-1449 edition 3 and ISO standards. The fail mode of an MOV is to short and turn into a ball of plasma, much faster than a circuit breaker can react. Where I worked at we isolated phases and fuses with mica, to give the fuse time to pop and stop a disaster.

NOTE: MOVS intentionally have a soft clamp curve, as AC power is loosely regulated at best. Thus the high clamp voltage which MUST be greater than the highest expected AC + DC peak. UL and ISO enforce this attribute along with use of fast-blow platinum fuses. 15 A for 20 mm MOVS and 30 A for 32 and 40 mm MOVS.

Industrial (and large houses) make use of parallel 32 mm or 40 mm MOVS from phase to phase, phase to neutral, phase to ground and neutral to ground. For delta units with no neutral or a WYE with poor neutral, the phase to ground MOVS are double voltage. Phases are isolated with mica sheets and packed with fine quartz sand to absorb heat and exploding MOVS. This is sealed with a rubber-like epoxy.

To protect commercial circuit boards use 20 mm MOVS from line to neutral (120 VAC) or line to line for 240 VAC. Add a MOV from line to ground and you are done. Be sure to use a fast-blow fuse on each hot line, 15 amps or less. That is all you need for DIY products not being sold to the public.

  • \$\begingroup\$ @Chester Gillon Thanks for the table. I am stuck using a cellphone as my PC \$\endgroup\$
    – Sparky256
    Jan 28 at 20:34
  • \$\begingroup\$ Thanks for your input! I have been looking at the V275LA40AP as a viable solution for the L-N clamping as well, accepting the increased voltage during a surge in 110V operation. This device will be residential only, not industrial (the test lab just likes to test on industrial levels as a quality mark for the customer, unless it fails then they go down to residential), so I think this should be fine. When the MOV fails, it shorts, so the already present 100mA/200mA slo-blo fuse on L should trigger as in any other overcurrent scenario? \$\endgroup\$
    – zloopy
    Jan 29 at 14:35
  • \$\begingroup\$ You should consider fast-blow fuses, even if you have to increase their amp rating. \$\endgroup\$
    – Sparky256
    Jan 29 at 15:19

I can't speak to the XLR shell/grounding as you haven't provided any information (schematics, mechanical diagrams) to support that, but regarding the mains section:

It almost certainly passes.

The transformer is a toroidal PC mount type, 15VA capacity, rated 4kV isolation (test duration not stated), 500mA output, and 18.5V OC + 3.1Ω. Primary resistance is unstated, but it's probably equal (winding-referred), as dissimilar cross-section in the windings would be wasteful. We could also turn total efficiency into a rough resistance figure. Turns ratio is 115/18.5 and impedance goes as the square or 38.6 times, or 120Ω primary.

There will be some leakage inductance as well, though as a toroidal type, it may be relatively small. Probably it is still dominant at surge time scales, but if we can make do with resistance alone, even better.

2kV surge, applied common-mode (line-ground), is trivially handled by the isolation rating. 2kV differential (line-line) remains a concern. IEC 61000-4-5 surge has a source impedance of 2Ω (sort of). We have effectively 240Ω in series with it (primary-referred), reducing peak current to less than 10A, or 62A secondary-referred.

Typical 1500µF capacitors have ESR in the low 100s mΩ, and mid 10s are available. The surge current causes an immediate increase in terminal voltage due to ESR, on the order of 10V, along with a gradual increase as the capacitance gets charged. Supposing it's a square pulse of 50µs duration, 62A delivers 3.1mC, which distributed into 6mF total, is a change of 0.52V. So the ESR will be dominant, at least until very low ESR values.

Regarding your SPICE model, it lacks a LISN or other coupling network; you've simply shorted out the surge source into the mains voltage source. Surge is typically coupled in series, using a transformer of modest inductance to still pass mains current. Your transformer model lacks DCR and leakage inductance, both of which are significant per above. With these changes, and realistic ESR of the capacitors, you should find reasonable waveforms, and regulator ratings are respected.

  • \$\begingroup\$ Hello Tim, thank you for your thorough response! I updated the question with ESR and leakage inductance values and added some more clarification to the spice sim. I also added new sim results with leakage inductance and it appears that there is no surge remaining on the secondary? I do struggle with proper AC/CDN simulation values though. As for the surge source: AFAIK looking at the 61000-4-5 spec, the combination generator seems indeed strapped across L-N during the line-line test? \$\endgroup\$
    – zloopy
    Jan 29 at 14:20
  • \$\begingroup\$ A CDN is not given by design, but rather by compliance with the calibration parameters; typical values for this would be some 100s uH, uncoupled. Values can be calculated and confirmed with SPICE, with a setup to measure OCV and SCC of the generator + network. You put in a common mode choke, which still partially shorts out the differential mode surge. \$\endgroup\$ Jan 29 at 15:00
  • \$\begingroup\$ Ah you are right. I misinterpreted the CDN drawing. Removing the K coupling, returns some current on the secondary. But its only around 0.5A on the 1500uF caps. Is it possible to deduct a plausible outcome from this? Even considering the CDN and ESR values are potentially off? \$\endgroup\$
    – zloopy
    Jan 29 at 16:10
  • \$\begingroup\$ How did you arrive at the values L7, L8? Also magnetizing inductance (L1-L4) probably should be much larger, though that won't affect surge. \$\endgroup\$ Jan 29 at 17:31
  • \$\begingroup\$ Measured all inductance with a LCR meter. Shorted the other side for leakage measurement. \$\endgroup\$
    – zloopy
    Jan 29 at 18:25

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