# Power cycling circuit

I am designing a circuit which may fail to start up. It has a power good output which is high when the supply is working. When the power good output goes low, the circuit has failed to start oscillating properly, and needs to be restarted. I thought about using a 555 timer but couldn't figure out how to make the output stay high when the input signal was low. Any ideas?

The circuit must do this because it fails to start under high current set points. It drives an LED. The idea is at higher currents the output folds back, but doesn't require an actual restart of the circuit to get it working again, and the fold-back mechanism makes the LED blink on and off.

Here's an image to show what I mean. Green shows the LED current. It has been set too high and the supply's overvoltage protection circuit kicks in to prevent more than 4.7V being applied across the LED (to prevent breakdown of the LED if in reverse.) The blue trace represents the power good output. During the oscillations the supply is outputting correctly, so it is high. It drops low after the oscillations stop. A short delay after it drops low, I need the supply to reset and try again - this would be accomplished by turning the supply controller IC on and off.

You want a low-going "power good" to temporarily turn off the supply.

This circuit will do what you want. Choose R and C to get your desired delay.

Edit: there should probably be a resistor between the PNP base and NPN collector instead of a direct connection as shown.

• I love a man whom knows his analog design! Commented Nov 20, 2010 at 1:36
• I tried your circuit and couldn't get it working. The problem is when on, it only provides ~3V to the switcher IC, and it needs at least 6V to work properly. Any idea on why? Commented Nov 20, 2010 at 10:24
• What is Vcc? Which transistors did you use? What values of R and C? Commented Nov 20, 2010 at 15:58
• C = 1u, R = 1k, Vcc = ~6.5V. Commented Nov 21, 2010 at 20:13
• which transistors? Commented Nov 21, 2010 at 20:50

I would recommend the 555 timer. For the high/low problem, use a NOT gate. That way, the 555 gets to behave in its normal manner, and your PS gets the signal it needs.

• It feels like a waste to use a hex inverter IC, is there any way to invert the signal with a maximum output load of ~50mA? Commented Nov 20, 2010 at 0:30
• if you have any spare NOR or NAND in your circuit you can use that. Or a common-emitter transistor and two resistors. Commented Nov 20, 2010 at 0:36
• Try an inverting op amp. Set the non-inverting side to halfway between logic 0 and 1 using a resistor divider, and feed the inverting side directly from the 555. Commented Nov 20, 2010 at 0:40
• A FET gate that draws 50 mA DC? I'm confused. Can you sketch the schematic and post it? Commented Nov 20, 2010 at 0:44
• I went for that just for simplicity of design. You could also use an NPN. Ground the emitter. You may need a resistor on the base to control base current. (As long as it saturates, it's got enough.) Supply the collector through a suitable resistor which will allow 50ma at logic 1 to your reset line. Connect the reset line (output) at the collector. Commented Nov 20, 2010 at 0:46