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I am tracing my first DDR2 with Cyclone V PCB and I can't find exact information about CLK vs DSQ vs ADR length matching.

External Memory Interface Handbook Volume 2: Design Guidelines from Intel says that: "All data, address, and command signals must have matched length traces ± 50 ps.", but about Clock: "equal to the signals in the Address/ Command Group or up to 100 mils (2.54 mm) longer than the signals in the Address/Command Group."

AMD support (https://support.xilinx.com/s/question/0D52E00006hpORASA2/dqsdqs-to-ckck-skew-limit-for-ddr2) says: "The maximum electrical delay between any DQS/DQS # and CK/CK # must be < ±25 ps."

Microchip (https://onlinedocs.microchip.com/pr/GUID-2952C8AA-A592-489E-8058-3FD06065EDDB-en-US-2/index.html?GUID-9420BB25-4489-441C-B9D0-9283388BBAF9) says: "Match DQS to clock loosely Yes" for DDR2.

But when I am looking at real designs Address and Clock lines used to be longer than DQS.

At Altera Cyclone IV GX FPGA Development Kit: Data lines are 28-40mm, Clock 47mm, Address lines are 46-58mm.

At SO-DIMM module reference layout from JEDEC: Data lines are about 17mm, Clock is 27mm, Address lines are about 56 mm.

All byte lanes matches with their DQS.
All DQS matches between each other.
But what about CLK vs DSQ vs ADR?

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The first thing to realize is that clock speed and the manufacturer will determine matching lengths. They all have different specs, so design with the memory controllers specs in their datasheets. (If you have intel, then use their specs. The signal propagation delay can be calculated if you know the Er and Dk of your substrate and the tranmission line properties: https://www.protoexpress.com/blog/signal-propagation-delay-pcb/

But what about CLK vs DSQ vs ADR?

Usually any ddr routing timing is done in this order:
1)Clocks (longest)
2)Address (less length than clock)
3)Data (less length than address)

The clocks should be the longest, because they happen last, the address and data must be set before the main clock. The address must be set before the data is transferred. The data has it's own clock that needs to be matched to the data.

This diagram is for DDR3 but the principles apply to DDR2.
enter image description here
Source: https://fedevel.com/blog/ddr3-length-matching-rules

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  • \$\begingroup\$ Thank you a lot for your answer. The picture is very good and clear but it, unfortunately not answers exactly my question: For DDR3 Data length vs Clock length is not defined, as it's shown there. But for DDR2 it's important as I understand. Everywhere is written that they should match loosely. Also in Intel document says that same rules applies for: • DIMM—UDIMM topology • DIMM—RDIMM topology • Discrete components laid out in UDIMM topology • Discrete components laid out in RDIMM topology However DIMM module already have traces with different trace lengths. \$\endgroup\$ Commented Jan 29 at 22:13
  • \$\begingroup\$ Or does "Discrete components laid out in UDIMM topology" also describes length difference? \$\endgroup\$ Commented Jan 29 at 22:14
  • \$\begingroup\$ Usually what I do is match length everything and put the clock a few ps ahead and then address and then data is much looser, which isn't hard to do with modern PCBCAD. The more margin you have on the matching the better the design will be. Most PCBCAD will also let you plug in the package length so if there is differences in the package/module you can account for that in the traces between the memory controller and memory. Make a length budget and do some simple routes and see if it's doable with the constraints you have. \$\endgroup\$
    – Voltage Spike
    Commented Jan 29 at 22:20
  • \$\begingroup\$ The UDIMM module should tell you what the trace lengths are matched to, or you should contact the manufacturer and ask them. \$\endgroup\$
    – Voltage Spike
    Commented Jan 29 at 22:21

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