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I am designing a circuit involving an LTC4316, which is configured by providing one of sixteen analog voltages on each of the XORH and XORL pins to set the upper and lower nibbles of its configuration byte (which for the specific chip, is the I2C address translation mask).

Ordinarily, for a device with a single fixed I2C address, I would follow the procedure laid out in the datasheet to arrive at appropriate resistor values for a resistor divider. However, for this device, this needs to be settable by the user or installer. My prototype involved using a potentiometer and providing test points for the user to probe to set the voltage, but this is not a very user-friendly procedure; it would be much better to provide a set of discrete DIP switches and some passive resistors.

The datasheet provides the following table for what voltage ratio the configuration pin needs to be placed at for the different configuration values:

| addr | ratio Vin/Vcc  |
| ---- | -------------- |
| 0000 | ≤ 0.03125      |
| 0001 | 0.09375 ±0.015 |
| 0010 | 0.15625 ±0.015 |
| 0011 | 0.21875 ±0.015 |
| 0100 | 0.28125 ±0.015 |
| 0101 | 0.34375 ±0.015 |
| 0110 | 0.40625 ±0.015 |
| 0111 | 0.46875 ±0.015 |
| 1000 | 0.53125 ±0.015 |
| 1001 | 0.59375 ±0.015 |
| 1010 | 0.65625 ±0.015 |
| 1011 | 0.71875 ±0.015 |
| 1100 | 0.78125 ±0.015 |
| 1101 | 0.84375 ±0.015 |
| 1110 | 0.90625 ±0.015 |
| 1111 | ≥ 0.96875      |

(Note that these are not volts, they're unitless multiples of the input supply voltage.)

Essentially, this is just splitting the range between 0.0 to 1.0 into 16 equal intervals, with the 0.015 tolerance allowing you to hit anywhere in the middle 48% of each interval.

The input impedance of the pins here is really very high -- the datasheet's table also includes recommendations for resistances in a fixed divider, and for e.g. 0111 it recommends using an 887k / 1M.

Note that the voltage levels I need to achieve are not ones I am able to specify myself. There is no programmable uC, and there are no additional voltage supplies other than Vcc and ground.

Technically, I don't need the dip switch positions to map neatly to separate bits. The board already has a silkscreened table of DIP switch positions vs the translated addresses of the on-board devices, and this table can be shuffled into any order if there's a clever scheme that can produce these voltages in some order other than the usual one.

An R-2R ladder would be able to achieve a compatible set of evenly-spaced voltages, but the classic design requires inputs driven both to the high and low voltages -- meaning more expensive dual-throw DIP switches rather than the common single-throw type. Given the high input impedance, using low-value pullups and high-value ladder resistance values could work, but irritatingly the voltages an R2R ladder produces are off by half a step, going from one rail to one step shy of the other rather than something from the middle 48% of each step.

An arrangement that makes use of only a small number of distinct resistor values would be nice, but resistors are cheap -- and as long as I can make do with only basic values, having them assembled is cheap too.

How can I achieve this type of analog voltage configuration in a way that's settable from a DIP switch, using only passive resistance values?

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  • \$\begingroup\$ Is adding a quad buffer / inverter out of the question? This would allow SPST switches and R2R DAC. \$\endgroup\$
    – Transistor
    Commented Jan 30 at 12:55
  • \$\begingroup\$ @Transistor it's not totally out of the question, and I suppose that'd probably be cheaper than using SPDT switches. Though, come to think of it it's probably even possible with just some low value pullups and high value R2R resistors -- since that the input impedance here is really quite high (the table I excerpted the voltages from also recommends a 1000k / 887k divider when programming 0111). \$\endgroup\$ Commented Jan 30 at 13:05
  • \$\begingroup\$ Sounds like a job for a Python or MATLAB. Are you constrained to E24 resistors? How many can you afford (space-wise)? \$\endgroup\$
    – winny
    Commented Jan 30 at 13:10
  • \$\begingroup\$ @winny I believe I'll need 1% tolerance resistors to achieve the 0.015 voltage tolerances anyway, so theoretically any E96 value should be available -- but on the flip side, it'd be really nice if it could be done using only the 1% resistors on JLC's "Basic Parts" list, to limit setup costs for smaller assembly runs. \$\endgroup\$ Commented Jan 30 at 13:21
  • \$\begingroup\$ I have an elegant-looking plan, but it involves 8 SPST DIP switches per nibble, which is as many as an R2R ladder would use, as many resistors as well, so no great inclination to post it as an answer. Would the extra space for 8 SPST DIPs outweigh the extra cost of 4 SPDT switches? \$\endgroup\$
    – Neil_UK
    Commented Jan 30 at 13:55

5 Answers 5

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CircuitLab / Imgur isn't working at the moment so here's an ASCII circuit.

           |
          (i) 16.6 uA
           |
    +------+--------> ADDR.
    |      |          0 - 1 V
   \ SW1   \
    \      / 1k
    |      \
    |      |
    +------+
    |      |
   \ SW2   \
    \      / 2k
    |      \
    |      |
    +------+
    |      |
   \ SW3   \
    \      / 4k
    |      \
    |      |
    +------+
    |      |
   \ SW4   \
    \      / 8k
    |      \
    |      |
    +------+- GND

By using a constant current source most of the complexity of the resistor divider can be eliminated - with the minor complexity of requiring a top-side constant current source.

The resistor chain can be made of 1, 2, 4 and 8 × 1k resistors which would keep the bill of materials simple at the expense of a few resistors and some PCB real-estate.

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    \$\begingroup\$ Arguably the CCS is desirable, as a VREF was not mentioned, or whether it can/should be ratiometric with the supply; in this case, an IREF is used instead. Which makes sense as resistors relate current to voltage; and conversely, a parallel-series circuit switching VREF into a bunch of resistors at zero load voltage would also do (series-parallel transformation, IREF <--> VREF, output having zero current <--> output having zero voltage). Of course the latter takes a transresistance amp to get back to an output voltage, so this is probably better. \$\endgroup\$ Commented Jan 30 at 14:05
  • \$\begingroup\$ Given that LT shows a minimum resistance value of 100K, this might be a problem for the CCS design. \$\endgroup\$
    – AnalogKid
    Commented Jan 30 at 14:22
  • \$\begingroup\$ @AnalogKid, yes, I'm not familiar with the chip. \$\endgroup\$
    – Transistor
    Commented Jan 30 at 14:28
  • \$\begingroup\$ @TimWilliams it does indeed need to be ratiometric -- the datasheet specifies the configuration voltages in terms of that ratio (Vx / Vcc), with the chip using its same supply as VREF. \$\endgroup\$ Commented Jan 30 at 15:18
  • \$\begingroup\$ @AnalogKid, I had another look through the datasheet and can't find the 100k minimum specification. I can't think why there would be one when it's a voltage reading input. \$\endgroup\$
    – Transistor
    Commented Jan 30 at 15:18
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using only passive resistance values?

I vote for the R-2R ladder approach.

The rungs of an R-2R ladder that are switched between two low-impedance voltages are the 2R components. I like the idea of an R-2R ladder with SPST switches pulling one direction and low-value resistors pulling the other. The problem is that the pull-down (for this discussion) resistors add to the 2R value in one logic polarity only. That is, they add to the 2R value in the down state, but not in the up state. This can be minimized by using low-value pull-down resistors but that increases circuit current, which could be a thing in a portable application.

The good news is that you already are driven to very high resistor values by the LT component. With 1% values of 499 K and 1 M, a 1 K pull-down resistor adds a 0.1% error to the rung impedance, way less than the percent voltage change per address value. The entire circuit requires 12 resistors, which can be implemented as three, 4-resistor networks: 3 - 499 K, 3 - 1.00 M, and 3 - 1.00 K. As above, a larger pull-down resistor decreases circuit current but increases the step value error. Life is choice.

The switch resistors can be either pull-up or pull-down, but I prefer pull-down. In this way, turning a switch on increases the output voltage, a more natural way of thinking.

Here is a high-resistance integrated network at Digi-Key. There might be others built for a 4-bit circuit that would be smaller. This is not a complete solution; the circuit still needs the pull-down resistors. But it does save space and reduces routing complexity.

https://www.digikey.com/en/products/detail/bourns-inc/4816P-R2R-474LF/4697551?s=N4IgjCBcodIMZQGYEMA2BnApgGhAeygG0QAmUgZgA4B2ANhAF08AHAFyhAGU2AnASwB2AcxABfPAE4ooRJFSZcBYiAqTSYUgAYmrDpG58hosaaA

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  • \$\begingroup\$ Yup, basically creating a D/A converter. One advantage is a unique output for every possible combo of closed switches. \$\endgroup\$ Commented Jan 30 at 16:37
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In order to get the outputs shown in the chart in the datasheet you can use the voltage divider and current source method as shown in another answer, but you need to use 5 resistors for the lower 4 bits and 4 resistors for the upper 3 bits.

For the lower 4 bits it would look something like this: enter image description here

The current source would be set to \$V_{CC}\times 31.25~uA\$

Example, with a \$V_{CC}\$ of 5 V the current would be 156.25 uA and with the switches all closed the \$V_{XORL}\$would be $$ 156.25~uA\times 1k = 0.15625~V $$ and \$V_{XORL}/V_{CC}\$ would be 0.03125 as shown in the datasheet chart.

Opening the switches would make that position a logic 1, with the 16k resistor being the high bit. For the upper 3 bits you'd use the same arrangement but leave out the 16k resistor.

If you have trouble getting a current source accurate enough at the nA level you could divide the resistor values by 10 or 100 and multiply the current by the same.

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This isn't exactly what you asked for, but is perhaps an alternative worth considering.

  • Instead of DIP switches, it uses a 2x11 header, with a shorting jumper installed in one of 16 positions (some horizontal, some vertical).
  • It needs 13 equal resistors (100K, perhaps), plus two resistors of 1.5x that value. (The 1.5x resistors could be replaced by a series/parallel combination of 1x resistors, so you could do this with 19 identical parts.)
  • You will presumably need two of these, to set both XORH and XORL. Note that you can use the same resistor ladder for both!

enter image description here

(I had hoped to be able to provide a solution using a 2x6 header - which has exactly 16 ways to plug a jumper into it. In fact, I can do a linear resistance choice that way, from 0R to 15R in 1R increments, but I couldn't think of any simple way to turn that resistance into the necessary resistance ratio.)

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    \$\begingroup\$ Ah! A man after my own heart. How to arrange combinations of plugs, especially canonical ones using all the possible arrangements). \$\endgroup\$
    – Neil_UK
    Commented Jan 31 at 13:54
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    \$\begingroup\$ How would you do the linear resistance with the 2x6 header? You could turn that into a voltage by using a current source instead of a voltage source. And I want to see your solution for that! \$\endgroup\$
    – Hearth
    Commented Jan 31 at 14:23
  • \$\begingroup\$ @Hearth: It's an extended version of an idea I had some years ago, for building a decade resistance substitution box using a 2x4 header (exactly 10 jumper positions!) per decade. Originally posted at eevblog.com/forum/projects/… . The "hexade"??? version should just continue the pattern for two more rows. \$\endgroup\$ Commented Jan 31 at 14:31
  • \$\begingroup\$ @Neil_UK, the images for my circuit are showing up for me. If you're talking about the original design that started that thread - it was a 2x10 header, with 9 Rs down one side, and the other side all connected together. \$\endgroup\$ Commented Jan 31 at 14:53
  • \$\begingroup\$ @Hearth A simple way to do 0-15 in a 4x2 would be a binary set in series, with a pin pair across each resistor. The following resistors in series - 1,3,3,3,3,2, have the unique property that you can select the resistance by choosing the goes-in and goes-out nodes, no jumpers required. This is especially useful if these are 4mm sockets, choose your digit value just with the connecting banana plug leads. \$\endgroup\$
    – Neil_UK
    Commented Jan 31 at 15:01
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I like Jason's answer. Note that an array of pins may well be smaller in board area than equivalent DIP switches. If the arrangement is relatively permanent, then you don't need to fit the pins, and can program with solder blobs between the pin pads. If the board has a likely default setting, then it can be manufactured with a small trace across the 'on' gaps, to be Dremelled or scalpelled out if reprogramming is needed.

Solution for 2 rows of 8 pins, with 4 shorting links, that go only between the rows (so simple to silk-screen the instructions on). This was inspired by the switching inside my 4-decade precision voltage divider box. All the jumpers must be connected, so there's no 'where to store the unused jumpers' issue.

schematic

simulate this circuit – Schematic created using CircuitLab

You keep exactly 4 jumpers connected, and move a jumper between its H and L position, which 'moves' the corresponding resistor between the top and bottom of the potential divider.

Here's a solution for 2 rows 6 pins, or two 'stars' of 5 pins (as each set of switches shares a common connection), with two jumpers always used. It's basically a two quaternary digit DAC.

schematic

simulate this circuit

The Vpad resistors are to get the end voltages correct, I'm not sure I fully understand the tolerances for the 0000 and 1111 programming voltages.

The Rout_pad resistors are to equalise the output impedance of the outer two states with the inner two, so that when the DAC is loaded by the other one, there will be no digit-dependent interaction. These resistors are all equal.

Choose the R_MSD and R_LSD resistors so that one DAC has 16x the weight of the other.

And finally, 4 rows of 3 pins, or equivalently 2 rows of 6 pins, will provide 4 SPDT 'switches' to program the standard R2R DAC ladder configuration.

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