Assume that an algorithm exists in C language. It needs to be implemented in VHDL. One way to compare the two is to apply stimulus from file to model using another program or script and then store the outputs into a file. Then, in the RTL simulation, use same file for stimulus and compare the outputs with those stored in file from the C model.

This is how I have done it in the past. However, assume that the model is complex and I want to run the simulation for a very long time and apply pseudorandom stimulus. Is there a way to have the C model in the same simulation as the VHDL RTL entity and make comparison between the two?

The problem is simple. The VHDL does not understand C model or how to interact with it so it cannot be instantiated in the testbench itself. So maybe the simulation program will need to be controlled in some way using TCL or otherwise.


1 Answer 1


The literal answer is yes.

Step back from the VHDL centric view.

1. Use a third script or program to control both simulations

You can use the VHDL simulator to read from the same input as the C program.

Then use that third script or program to receive the outputs and compare them.

For example, GHDL announces: "Co-simulation with foreign applications is supported through Verilog Procedural Interface (VPI) and/or VHPIDIRECT." (Citation from the linked web site)

2. Combine both simulations in one C program

You can also strive to use the provided libghdl to include VHDL simulation in your C driver program.

Similarly you can rebuild your C simulation as a library to keep concerns separated.

In any case, be aware of small differences in propagation delays and other timing related effects.


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