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I plan to integrate a non-planar P⁺⁺/i/P⁺/N⁺⁺ avalanche photodiode (APD) array with a peripheral control circuit (e.g., trans-impedance amplifier, analog-to-digital converter, and quenching circuit) design using a standard CMOS process.

I know that an APD doping profile needs to be grown epitaxially, whereas, the p-MOS and n-MOS are fabricated using planar implantations.

I do not know whether or not the foundries like XFAB, Global Foundry, AMF, etc., can fabricate these hybrid doping stack devices on a single wafer. Or, the only option is to use 2.5D/3D integration? enter image description here I have contacted many foundries about this very question and so far, none of them have given me a direct answer.

I am also attaching an illustration to highlight the desired doping arrangement.

How could I build a silicon stackup such as this?

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For foundries to process the design, especially at 0.13μm tech node, all the devices must be planar. That means the previous structures will not be processed.

22nmFDSOI technology has the option to process these hybrid stacks.

A solution to fabricate the photodiode and the MOSFETs together using older tech nodes could be as follows:

enter image description here

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  • \$\begingroup\$ Interesting proposal, but I wonder how the doping depth compares with the optical absorption depth? \$\endgroup\$ Commented Feb 6 at 2:32
  • \$\begingroup\$ This is a design for an avalanche photodiode. That means, it has to be operated at a high applied bias such that impact ionization will be triggered at the P⁺⁺/N⁺ junction (multiplication junction). Plus, the P⁺⁺ layer in my design is ~0.15 μm, which enables a shallow multiplication junction. A shallow multiplication junction ensures decent absorption even for the shorter wavelengths (say ~450 nm) and a high field facilitates impact ionization and multiplication. I am working on simulating these devices. I can share the quantitative performance as and when the results are ready. \$\endgroup\$ Commented Feb 6 at 3:20

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