I plan to integrate a non-planar P⁺⁺/i/P⁺/N⁺⁺ avalanche photodiode (APD) array with a peripheral control circuit (e.g., trans-impedance amplifier, analog-to-digital converter, and quenching circuit) design using a standard CMOS process.
I know that an APD doping profile needs to be grown epitaxially, whereas, the p-MOS and n-MOS are fabricated using planar implantations.
I do not know whether or not the foundries like XFAB, Global Foundry, AMF, etc., can fabricate these hybrid doping stack devices on a single wafer. Or, the only option is to use 2.5D/3D integration? I have contacted many foundries about this very question and so far, none of them have given me a direct answer.
I am also attaching an illustration to highlight the desired doping arrangement.
How could I build a silicon stackup such as this?